From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Lutomirski Subject: Re: [PATCH 2/3] drm/intel: Attempt to use 10-bit gamma palette mode Date: Mon, 26 Apr 2010 21:09:48 -0400 Message-ID: References: <1272320445.23864.4.camel@pcjc2lap> <1272320658-2157-2-git-send-email-pcjc2@cam.ac.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-pv0-f177.google.com (mail-pv0-f177.google.com [74.125.83.177]) by gabe.freedesktop.org (Postfix) with ESMTP id CAA9A9E75B for ; Mon, 26 Apr 2010 18:10:08 -0700 (PDT) Received: by pvf33 with SMTP id 33so988441pvf.36 for ; Mon, 26 Apr 2010 18:10:08 -0700 (PDT) In-Reply-To: <1272320658-2157-2-git-send-email-pcjc2@cam.ac.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Peter Clifton Cc: "intel-gfx@lists.freedesktop.org" List-Id: intel-gfx@lists.freedesktop.org Should this patch be enough to output 10 bits/channel on a digital output? I just ordered some 10-bit monitors and it would be fun to use them in all their high-precision glory? It should be relatively easy to use spotread (from Argyll) along with some hacked-up gamma loader to verify that it's working. --Andy On Mon, Apr 26, 2010 at 6:24 PM, Peter Clifton wrote: > --- > =A0drivers/gpu/drm/i915/i915_reg.h =A0 =A0 =A0| =A0 =A07 ++++++- > =A0drivers/gpu/drm/i915/intel_display.c | =A0 33 ++++++++++++++++++++++++= ++------- > =A02 files changed, 32 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index ab1bd2d..7a0c6ac 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1766,6 +1766,9 @@ > =A0#define =A0 PIPECONF_INTERLACE_W_FIELD_INDICATION =A0 =A0 =A0 =A0(6 <<= 21) > =A0#define =A0 PIPECONF_INTERLACE_FIELD_0_ONLY =A0 =A0 =A0 =A0 =A0 =A0 = =A0(7 << 21) > =A0#define =A0 PIPECONF_CXSR_DOWNCLOCK =A0 =A0 =A0(1<<16) > +#define PIPEAGCMAXRED =A0 =A0 =A0 =A0 =A00x70010 > +#define PIPEAGCMAXGREEN =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00x70014 > +#define PIPEAGCMAXBLUE =A0 =A0 =A0 =A0 0x70018 > =A0#define PIPEASTAT =A0 =A0 =A0 =A0 =A0 =A0 =A00x70024 > =A0#define =A0 PIPE_FIFO_UNDERRUN_STATUS =A0 =A0 =A0 =A0 =A0 =A0(1UL<<31) > =A0#define =A0 PIPE_CRC_ERROR_ENABLE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0(1UL<<29) > @@ -1958,13 +1961,15 @@ > =A0/* Pipe B */ > =A0#define PIPEBDSL =A0 =A0 =A0 =A0 =A0 =A0 =A0 0x71000 > =A0#define PIPEBCONF =A0 =A0 =A0 =A0 =A0 =A0 =A00x71008 > +#define PIPEBGCMAXRED =A0 =A0 =A0 =A0 =A00x71010 > +#define PIPEBGCMAXGREEN =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00x71014 > +#define PIPEBGCMAXBLUE =A0 =A0 =A0 =A0 0x71018 > =A0#define PIPEBSTAT =A0 =A0 =A0 =A0 =A0 =A0 =A00x71024 > =A0#define PIPEBFRAMEHIGH =A0 =A0 =A0 =A0 0x71040 > =A0#define PIPEBFRAMEPIXEL =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00x71044 > =A0#define PIPEB_FRMCOUNT_GM45 =A0 =A00x71040 > =A0#define PIPEB_FLIPCOUNT_GM45 =A0 0x71044 > > - > =A0/* Display B control */ > =A0#define DSPBCNTR =A0 =A0 =A0 =A0 =A0 =A0 =A0 0x71180 > =A0#define =A0 DISPPLANE_ALPHA_TRANS_ENABLE =A0 =A0 =A0 =A0 (1<<15) > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index 456f738..5e8191a 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -3433,6 +3433,9 @@ void intel_crtc_load_lut(struct drm_crtc *crtc) > =A0 =A0 =A0 =A0int pipe =3D intel_crtc->pipe; > =A0 =A0 =A0 =A0int pal_reg =3D (pipe =3D=3D 0) ? PALETTE_A : PALETTE_B; > =A0 =A0 =A0 =A0int pipeconf_reg =3D (pipe =3D=3D 0) ? PIPEACONF : PIPEBCO= NF; > + =A0 =A0 =A0 int maxr_reg =3D (pipe =3D=3D 0) ? PIPEAGCMAXRED : PIPEBGCM= AXRED; > + =A0 =A0 =A0 int maxg_reg =3D (pipe =3D=3D 0) ? PIPEAGCMAXGREEN : PIPEBG= CMAXGREEN; > + =A0 =A0 =A0 int maxb_reg =3D (pipe =3D=3D 0) ? PIPEAGCMAXBLUE : PIPEBGC= MAXBLUE; > =A0 =A0 =A0 =A0int pipeconf =3D I915_READ(pipeconf_reg); > =A0 =A0 =A0 =A0int i; > > @@ -3445,17 +3448,33 @@ void intel_crtc_load_lut(struct drm_crtc *crtc) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0pal_reg =3D (intel_crtc->pipe =3D=3D 0) ? = LGC_PALETTE_A : > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0LGC_PALETTE_B; > > - =A0 =A0 =A0 /* Switch to 8-bit gamma mode */ > - =A0 =A0 =A0 pipeconf &=3D ~PIPEACONF_GAMMA; > + =A0 =A0 =A0 /* Switch to 10-bit gamma mode */ > + =A0 =A0 =A0 pipeconf |=3D PIPEACONF_GAMMA; > =A0 =A0 =A0 =A0I915_WRITE(pipeconf_reg, pipeconf); > =A0 =A0 =A0 =A0I915_READ(pipeconf_reg); > > - =A0 =A0 =A0 for (i =3D 0; i < 256; i++) { > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 I915_WRITE(pal_reg + 4 * i, > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0((intel_crtc->lut_r[= i] >> 8) << 16) | > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0((intel_crtc->lut_g[= i] >> 8) << 8) | > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(intel_crtc->lut_b[i= ] >> 8)); > + =A0 =A0 =A0 /* Use every other value from the LUT passed, > + =A0 =A0 =A0 =A0* 10-bit mode uses 128 entries. */ > + =A0 =A0 =A0 for (i =3D 0; i < 128; i++) { > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 I915_WRITE(pal_reg + 8 * i, > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0((intel_crtc->lut_r[= 2 * i] & 0xFF) << 16) | > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0((intel_crtc->lut_g[= 2 * i] & 0xFF) << 8) | > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(intel_crtc->lut_b[2= * i] & 0xFF)); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 I915_WRITE(pal_reg + 8 * i + 4, > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0((intel_crtc->lut_r[= 2 * i] >> 8) << 16) | > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0((intel_crtc->lut_g[= 2 * i] >> 8) << 8) | > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(intel_crtc->lut_b[2= * i] >> 8)); > =A0 =A0 =A0 =A0} > + > + =A0 =A0 =A0 /* FIXME: Distortion here, we're trying to get 129 evenly s= paced > + =A0 =A0 =A0 =A0* samples from a LUT with 256 entries. We use 0, 2, 4 ..= . 254, > + =A0 =A0 =A0 =A0* for the main palette, then entry 255 for this last reg= ister. > + =A0 =A0 =A0 =A0*/ > + =A0 =A0 =A0 /* Note that these registers _could_ take the LUT value of > + =A0 =A0 =A0 =A0* 1024, but we're maxing out at 1023.984375 as it is eas= ier. */ > + =A0 =A0 =A0 I915_WRITE(maxr_reg, intel_crtc->lut_r[255]); > + =A0 =A0 =A0 I915_WRITE(maxg_reg, intel_crtc->lut_g[255]); > + =A0 =A0 =A0 I915_WRITE(maxb_reg, intel_crtc->lut_b[255]); > =A0} > > =A0static int intel_crtc_cursor_set(struct drm_crtc *crtc, > -- > 1.7.0.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx >