From: Lucas De Marchi <lucas.demarchi@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-xe@lists.freedesktop.org
Subject: Re: [Intel-xe] [PATCH 6/8] drm/xe/irq: Drop remaining "gen11_" prefix from IRQ functions
Date: Fri, 31 Mar 2023 15:26:41 -0700 [thread overview]
Message-ID: <20230331222641.h3ik4f266qrx4eut@ldmartin-desk2.lan> (raw)
In-Reply-To: <20230330182405.43993-7-matthew.d.roper@intel.com>
On Thu, Mar 30, 2023 at 11:24:03AM -0700, Matt Roper wrote:
>The remaining "gen11_*" IRQ functions are common to all platforms
>supported by the Xe driver. Drop the unnecessary prefix.
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/xe/xe_irq.c | 46 ++++++++++++++++++-------------------
> 1 file changed, 22 insertions(+), 24 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>index de0c27c0a09c..9fac03b63e7e 100644
>--- a/drivers/gpu/drm/xe/xe_irq.c
>+++ b/drivers/gpu/drm/xe/xe_irq.c
>@@ -84,7 +84,7 @@ static u32 xelp_intr_disable(struct xe_gt *gt)
> }
>
> static u32
>-gen11_gu_misc_irq_ack(struct xe_gt *gt, const u32 master_ctl)
>+gu_misc_irq_ack(struct xe_gt *gt, const u32 master_ctl)
> {
> u32 iir;
>
>@@ -105,7 +105,7 @@ static inline void xelp_intr_enable(struct xe_gt *gt, bool stall)
> xe_mmio_read32(gt, GFX_MSTR_IRQ.reg);
> }
>
>-static void gen11_gt_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
>+static void gt_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> {
> u32 irqs, dmask, smask;
> u32 ccs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE);
>@@ -172,7 +172,7 @@ static void xelp_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> {
> /* TODO: PCH */
>
>- gen11_gt_irq_postinstall(xe, gt);
>+ gt_irq_postinstall(xe, gt);
>
> unmask_and_enable(gt, GU_MISC_IRQ_REGS, GU_MISC_GSE);
>
>@@ -180,10 +180,10 @@ static void xelp_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> }
>
> static u32
>-gen11_gt_engine_identity(struct xe_device *xe,
>- struct xe_gt *gt,
>- const unsigned int bank,
>- const unsigned int bit)
>+gt_engine_identity(struct xe_device *xe,
>+ struct xe_gt *gt,
>+ const unsigned int bank,
>+ const unsigned int bit)
> {
> u32 timeout_ts;
> u32 ident;
>@@ -216,7 +216,7 @@ gen11_gt_engine_identity(struct xe_device *xe,
> #define OTHER_MEDIA_GUC_INSTANCE 16
>
> static void
>-gen11_gt_other_irq_handler(struct xe_gt *gt, const u8 instance, const u16 iir)
>+gt_other_irq_handler(struct xe_gt *gt, const u8 instance, const u16 iir)
> {
> if (instance == OTHER_GUC_INSTANCE && !xe_gt_is_media_type(gt))
> return xe_guc_irq_handler(>->uc.guc, iir);
>@@ -230,9 +230,9 @@ gen11_gt_other_irq_handler(struct xe_gt *gt, const u8 instance, const u16 iir)
> }
> }
>
>-static void gen11_gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
>- u32 master_ctl, long unsigned int *intr_dw,
>- u32 *identity)
>+static void gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
>+ u32 master_ctl, long unsigned int *intr_dw,
>+ u32 *identity)
> {
> unsigned int bank, bit;
> u16 instance, intr_vec;
>@@ -249,9 +249,8 @@ static void gen11_gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
> intr_dw[bank] =
> xe_mmio_read32(gt, GT_INTR_DW(bank).reg);
> for_each_set_bit(bit, intr_dw + bank, 32)
>- identity[bit] = gen11_gt_engine_identity(xe, gt,
>- bank,
>- bit);
>+ identity[bit] = gt_engine_identity(xe, gt,
>+ bank, bit);
> xe_mmio_write32(gt, GT_INTR_DW(bank).reg,
> intr_dw[bank]);
> }
>@@ -262,8 +261,7 @@ static void gen11_gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
> intr_vec = INTR_ENGINE_INTR(identity[bit]);
>
> if (class == XE_ENGINE_CLASS_OTHER) {
>- gen11_gt_other_irq_handler(gt, instance,
>- intr_vec);
>+ gt_other_irq_handler(gt, instance, intr_vec);
> continue;
> }
>
>@@ -296,11 +294,11 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
> return IRQ_NONE;
> }
>
>- gen11_gt_irq_handler(xe, gt, master_ctl, intr_dw, identity);
>+ gt_irq_handler(xe, gt, master_ctl, intr_dw, identity);
>
> xe_display_irq_handler(xe, master_ctl);
>
>- gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
>+ gu_misc_iir = gu_misc_irq_ack(gt, master_ctl);
>
> xelp_intr_enable(gt, false);
>
>@@ -338,7 +336,7 @@ static void dg1_intr_enable(struct xe_device *xe, bool stall)
>
> static void dg1_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> {
>- gen11_gt_irq_postinstall(xe, gt);
>+ gt_irq_postinstall(xe, gt);
>
> unmask_and_enable(gt, GU_MISC_IRQ_REGS, GU_MISC_GSE);
>
>@@ -388,12 +386,12 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
>
> if (!xe_gt_is_media_type(gt))
> xe_mmio_write32(gt, GFX_MSTR_IRQ.reg, master_ctl);
>- gen11_gt_irq_handler(xe, gt, master_ctl, intr_dw, identity);
>+ gt_irq_handler(xe, gt, master_ctl, intr_dw, identity);
> }
>
> xe_display_irq_handler(xe, master_ctl);
>
>- gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
>+ gu_misc_iir = gu_misc_irq_ack(gt, master_ctl);
>
> dg1_intr_enable(xe, false);
>
>@@ -402,7 +400,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> return IRQ_HANDLED;
> }
>
>-static void gen11_gt_irq_reset(struct xe_gt *gt)
>+static void gt_irq_reset(struct xe_gt *gt)
> {
> u32 ccs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE);
> u32 bcs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
>@@ -448,7 +446,7 @@ static void xelp_irq_reset(struct xe_gt *gt)
> {
> xelp_intr_disable(gt);
>
>- gen11_gt_irq_reset(gt);
>+ gt_irq_reset(gt);
>
> mask_and_disable(gt, GU_MISC_IRQ_REGS);
> mask_and_disable(gt, PCU_IRQ_REGS);
>@@ -459,7 +457,7 @@ static void dg1_irq_reset(struct xe_gt *gt)
> if (gt->info.id == 0)
> dg1_intr_disable(gt_to_xe(gt));
>
>- gen11_gt_irq_reset(gt);
>+ gt_irq_reset(gt);
>
> mask_and_disable(gt, GU_MISC_IRQ_REGS);
> mask_and_disable(gt, PCU_IRQ_REGS);
>--
>2.39.2
>
next prev parent reply other threads:[~2023-03-31 22:26 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-30 18:23 [Intel-xe] [PATCH 0/8] Interrupt cleanup and future-proofing Matt Roper
2023-03-30 18:23 ` [Intel-xe] [PATCH 1/8] drm/xe/irq: Drop gen3_ prefixes Matt Roper
2023-03-31 21:57 ` Lucas De Marchi
2023-03-30 18:23 ` [Intel-xe] [PATCH 2/8] drm/xe/irq: Add helpers to find ISR/IIR/IMR/IER registers Matt Roper
2023-03-31 22:08 ` Lucas De Marchi
2023-03-30 18:24 ` [Intel-xe] [PATCH 3/8] drm/xe/irq: Drop IRQ_INIT and IRQ_RESET macros Matt Roper
2023-03-30 18:24 ` [Intel-xe] [PATCH 4/8] drm/xe/irq: Drop unnecessary GEN11_ and GEN12_ register prefixes Matt Roper
2023-03-31 22:20 ` Lucas De Marchi
2023-03-31 22:45 ` Lucas De Marchi
2023-03-30 18:24 ` [Intel-xe] [PATCH 5/8] drm/xe/irq: Rename and clarify top-level interrupt handling routines Matt Roper
2023-03-31 22:25 ` Lucas De Marchi
2023-03-30 18:24 ` [Intel-xe] [PATCH 6/8] drm/xe/irq: Drop remaining "gen11_" prefix from IRQ functions Matt Roper
2023-03-31 22:26 ` Lucas De Marchi [this message]
2023-03-30 18:24 ` [Intel-xe] [PATCH 7/8] drm/xe/irq: Drop commented-out code for non-existent media engines Matt Roper
2023-03-31 22:28 ` Lucas De Marchi
2023-03-30 18:24 ` [Intel-xe] [PATCH 8/8] drm/xe/irq: Don't clobber display interrupts on multi-tile platforms Matt Roper
2023-03-31 22:30 ` Lucas De Marchi
2023-03-30 18:26 ` [Intel-xe] ✓ CI.Patch_applied: success for Interrupt cleanup and future-proofing Patchwork
2023-03-30 18:26 ` [Intel-xe] ✗ CI.KUnit: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230331222641.h3ik4f266qrx4eut@ldmartin-desk2.lan \
--to=lucas.demarchi@intel.com \
--cc=intel-xe@lists.freedesktop.org \
--cc=matthew.d.roper@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).