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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?GwbLLSW+gNS8elhA8eRzbSOa5Z+nBfQ9tCNTJ+2W1cscy80akLXUJqQoV3fn?= =?us-ascii?Q?ovon2QRB989SAvdSn2b0YS0CDqgQZgLN351IXGA+TWMY4zzfy9vcpbnHVNjz?= =?us-ascii?Q?+IxDdtg/EUZr9umMsdWdaowhmp/ZALaopkuNZkdOhFs+pR3eAS+eeasvBgQ4?= =?us-ascii?Q?7AfGACRQv7cAdxn5mBtb1mV6NPHv4RgQ+adgd7RfJ14swWoybxqEVqmPLo6T?= =?us-ascii?Q?jM7pCrRfAsNpY7E1JWw4u5AdeXumAicSsYgZNC7Gu8k6u+UyaX7KAMOJZSAr?= =?us-ascii?Q?8XDkWgMIGfp1k9bFsF06BELFPIRUFK29gB4r+nhBirw4g1ZPPhUjgudoEFOv?= =?us-ascii?Q?T9DIct+MEBM9ohKPFnEP9Y1QZseWiJdZVgFaDI9Pl8VAou0XDMlqs6pgqVis?= =?us-ascii?Q?8ViICDSrw/s1wv9uJ88w8+LVcpZTh2f0sDInSxHXt7IBpGvtAH4lTY6uszbQ?= =?us-ascii?Q?L67QKhdi6FuJeUTgtDj9Ku/0jrGU7KRSLFSyYVz789JSQ94ig8gubRoq0H8u?= =?us-ascii?Q?VM49a9lu6i6tpivdcYXJvZZNA1SxMxn5+njZa9hMOVZqXIJAgiKctv158QNx?= =?us-ascii?Q?ySd7dz2bYJffqfv/I5SuE7+aQOWRq+yY3SEYjzteP9A55KJoIY5OwGinNcpJ?= =?us-ascii?Q?yO9WjBNFKtqq8xkQSlCMsVw3ztLl38ZkXr9z8y/6rXe56KNP2wjEtQIVL241?= =?us-ascii?Q?ivmigAF8iQr3WbeMQjPylxG4BXVH38HFjmyT3nEtBoNEUzfmhQP95c43tSDQ?= =?us-ascii?Q?4VFQZHCTdZpND3xrlXfmcWDUBK9UXegexTaG4RmQSr6WzUCR9BEirkJZMMFe?= =?us-ascii?Q?C0b+g8kgOHtre5V0vU+1QDbNWl1Q+IaRx6VvWUIQFTV2R1ctO2pdqKvHH1uN?= =?us-ascii?Q?HIxq7wJEt3iBHjAwBe+NJo3Oe9jU/s4/OMVGxjLIbv79eEogHVHzgNt4UKJf?= =?us-ascii?Q?EJeDFqB4dODx1SysyXAD+OU6NtErmcgJ0tzeewUHB5ZtUzukNkUknnL5U+iE?= =?us-ascii?Q?WZree0HnoT1dIla5zxX3RYsIUyIf2j+zIknsNzdgE0hX9GOGTs6VrFWVD/W7?= =?us-ascii?Q?eUFDkLIcbKuqZ8Jgb0YvSG/quPnT1zDLyAC2Bk2O0Q5DCeyifU/y6JM4IZzY?= =?us-ascii?Q?nRc8ROwsQCupjp1aCIrWtL7esJxhxi+QA1DDMVf2gVYoIiL9BrDyve2t5WeW?= =?us-ascii?Q?qORwCSv02OGWNfPwuIz2T3wk/xVhUOJqtBaCb6OHSVI3DT5a3TbYj7EFcSxD?= =?us-ascii?Q?gEI+pvDuO1jHxF6uE7WZcu7+wVR/NT5lBL+TFPw/1ZBB3QMjU31jwEU3Fu1C?= =?us-ascii?Q?9Ae3conAwV3s/J6D7lQpbfy3NXqw4PyYTmpyNzH0V98A3BJ9ydhJV4JK9Ku0?= =?us-ascii?Q?UnENQwl+HWeOCOam4h95R0wMohqL3MnWsoWTtpEU86fmEBRGbGIzpvLtPOTw?= =?us-ascii?Q?amqZjLl7DMebRl5+ub3d5nibhzbCT2CVrTUZ4gNUBmHKFHmd5ZHcfTNISyue?= =?us-ascii?Q?ogc7VbU1paKD0WErmAk4VjACcY6tQPFlPyFuVRieTZK5KA5+2ulQx27AZ5vU?= =?us-ascii?Q?vKzgiJmsb2tHWp3aJepW5bS4wGCHQPZ07uwxc8mA2fX1B9yIoT4bTAmiv+w+?= =?us-ascii?Q?tw=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 5fba314a-8406-4839-8734-08db32379a71 X-MS-Exchange-CrossTenant-AuthSource: CY5PR11MB6139.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Mar 2023 22:31:00.2042 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: yXuS3hqDmtcl2WVr6AR7ePIhIfCL3U1qPSPU0XpTc+2KUciL/9EEsXBHLUdXQSzAV0l15NFmMAlL99Y53B7eoLFOXDd5xqENLT5HLm4kb4M= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR11MB7433 X-OriginatorOrg: intel.com Subject: Re: [Intel-xe] [PATCH 8/8] drm/xe/irq: Don't clobber display interrupts on multi-tile platforms X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-xe@lists.freedesktop.org Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Thu, Mar 30, 2023 at 11:24:05AM -0700, Matt Roper wrote: >Although our only multi-tile platform today (PVC) doesn't support >display, it's possible that some future multi-tile platform will. >If/when this happens, display interrupts (both traditional display and >ASLE backlight interrupts raised as a Gunit interrupt) should be >delivered to the primary tile. Save away tile0's master_ctl value so >that it can still be used for display interrupt handling after the GT >loop. > >Signed-off-by: Matt Roper Reviewed-by: Lucas De Marchi Lucas De Marchi >--- > drivers/gpu/drm/xe/xe_irq.c | 14 +++++++++++--- > 1 file changed, 11 insertions(+), 3 deletions(-) > >diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c >index 02292e60e52c..636653f4e7ad 100644 >--- a/drivers/gpu/drm/xe/xe_irq.c >+++ b/drivers/gpu/drm/xe/xe_irq.c >@@ -347,7 +347,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg) > { > struct xe_device *xe = arg; > struct xe_gt *gt; >- u32 master_tile_ctl, master_ctl = 0, gu_misc_iir; >+ u32 master_tile_ctl, master_ctl = 0, tile0_master_ctl = 0, gu_misc_iir; > long unsigned int intr_dw[2]; > u32 identity[32]; > u8 id; >@@ -381,11 +381,19 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg) > if (!xe_gt_is_media_type(gt)) > xe_mmio_write32(gt, GFX_MSTR_IRQ.reg, master_ctl); > gt_irq_handler(xe, gt, master_ctl, intr_dw, identity); >+ >+ /* >+ * Save primary tile's master interrupt register for display >+ * processing below. >+ */ >+ if (id == 0) >+ tile0_master_ctl = master_ctl; > } > >- xe_display_irq_handler(xe, master_ctl); >+ xe_display_irq_handler(xe, tile0_master_ctl); > >- gu_misc_iir = gu_misc_irq_ack(gt, master_ctl); >+ /* Gunit GSE interrupts can trigger display backlight operations */ >+ gu_misc_iir = gu_misc_irq_ack(gt, tile0_master_ctl); > > dg1_intr_enable(xe, false); > >-- >2.39.2 >