From: Matt Roper <matthew.d.roper@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>, matthew.d.roper@intel.com
Subject: [Intel-xe] [PATCH v2 2/8] drm/xe/irq: Add helpers to find ISR/IIR/IMR/IER registers
Date: Fri, 31 Mar 2023 17:21:00 -0700 [thread overview]
Message-ID: <20230401002106.588656-3-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20230401002106.588656-1-matthew.d.roper@intel.com>
For cases where IRQ_INIT and IRQ_RESET are used, the relevant interrupt
registers are always consecutive and ordered ISR, IMR, IIR, IER. Adding
helpers to look these up from a base offset will let us eliminate some
of the CPP pasting and simplify other upcoming patches.
v2:
- s/_REGS/_OFFSET/ for consistency. (Lucas)
- Move IMR/IIR/IER helpers into xe_irq.c; they aren't needed anywhere
else. (Lucas)
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/regs/xe_regs.h | 11 ++---------
drivers/gpu/drm/xe/xe_irq.c | 32 +++++++++++++++++++------------
2 files changed, 22 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
index c1c829c23df1..be19b270c983 100644
--- a/drivers/gpu/drm/xe/regs/xe_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -76,15 +76,8 @@
#define SOFTWARE_FLAGS_SPR33 _MMIO(0x4f084)
-#define GEN8_PCU_ISR _MMIO(0x444e0)
-#define GEN8_PCU_IMR _MMIO(0x444e4)
-#define GEN8_PCU_IIR _MMIO(0x444e8)
-#define GEN8_PCU_IER _MMIO(0x444ec)
-
-#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
-#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
-#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
-#define GEN11_GU_MISC_IER _MMIO(0x444fc)
+#define PCU_IRQ_OFFSET 0x444e0
+#define GU_MISC_IRQ_OFFSET 0x444f0
#define GEN11_GU_MISC_GSE (1 << 27)
#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index d8fde8caff1e..f3f43d41a1b5 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -19,6 +19,14 @@
#include "xe_hw_engine.h"
#include "xe_mmio.h"
+/*
+ * Interrupt registers for a unit are always consecutive and ordered
+ * ISR, IMR, IIR, IER.
+ */
+#define IMR(offset) _MMIO(offset + 0x4)
+#define IIR(offset) _MMIO(offset + 0x8)
+#define IER(offset) _MMIO(offset + 0xc)
+
static void assert_iir_is_zero(struct xe_gt *gt, i915_reg_t reg)
{
u32 val = xe_mmio_read32(gt, reg.reg);
@@ -48,9 +56,9 @@ static void irq_init(struct xe_gt *gt,
}
#define IRQ_INIT(gt, type, imr_val, ier_val) \
irq_init((gt), \
- type##IMR, imr_val, \
- type##IER, ier_val, \
- type##IIR)
+ IMR(type), imr_val, \
+ IER(type), ier_val, \
+ IIR(type))
static void irq_reset(struct xe_gt *gt, i915_reg_t imr, i915_reg_t iir,
i915_reg_t ier)
@@ -67,7 +75,7 @@ static void irq_reset(struct xe_gt *gt, i915_reg_t imr, i915_reg_t iir,
xe_mmio_read32(gt, iir.reg);
}
#define IRQ_RESET(gt, type) \
- irq_reset((gt), type##IMR, type##IIR, type##IER)
+ irq_reset((gt), IMR(type), IIR(type), IER(type))
static u32 gen11_intr_disable(struct xe_gt *gt)
{
@@ -90,9 +98,9 @@ gen11_gu_misc_irq_ack(struct xe_gt *gt, const u32 master_ctl)
if (!(master_ctl & GEN11_GU_MISC_IRQ))
return 0;
- iir = xe_mmio_read32(gt, GEN11_GU_MISC_IIR.reg);
+ iir = xe_mmio_read32(gt, IIR(GU_MISC_IRQ_OFFSET).reg);
if (likely(iir))
- xe_mmio_write32(gt, GEN11_GU_MISC_IIR.reg, iir);
+ xe_mmio_write32(gt, IIR(GU_MISC_IRQ_OFFSET).reg, iir);
return iir;
}
@@ -173,7 +181,7 @@ static void gen11_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
gen11_gt_irq_postinstall(xe, gt);
- IRQ_INIT(gt, GEN11_GU_MISC_, ~GEN11_GU_MISC_GSE, GEN11_GU_MISC_GSE);
+ IRQ_INIT(gt, GU_MISC_IRQ_OFFSET, ~GEN11_GU_MISC_GSE, GEN11_GU_MISC_GSE);
gen11_intr_enable(gt, true);
}
@@ -336,7 +344,7 @@ static void dg1_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
{
gen11_gt_irq_postinstall(xe, gt);
- IRQ_INIT(gt, GEN11_GU_MISC_, ~GEN11_GU_MISC_GSE, GEN11_GU_MISC_GSE);
+ IRQ_INIT(gt, GU_MISC_IRQ_OFFSET, ~GEN11_GU_MISC_GSE, GEN11_GU_MISC_GSE);
if (gt->info.id == XE_GT0)
dg1_intr_enable(xe, true);
@@ -441,8 +449,8 @@ static void gen11_irq_reset(struct xe_gt *gt)
gen11_gt_irq_reset(gt);
- IRQ_RESET(gt, GEN11_GU_MISC_);
- IRQ_RESET(gt, GEN8_PCU_);
+ IRQ_RESET(gt, GU_MISC_IRQ_OFFSET);
+ IRQ_RESET(gt, PCU_IRQ_OFFSET);
}
static void dg1_irq_reset(struct xe_gt *gt)
@@ -452,8 +460,8 @@ static void dg1_irq_reset(struct xe_gt *gt)
gen11_gt_irq_reset(gt);
- IRQ_RESET(gt, GEN11_GU_MISC_);
- IRQ_RESET(gt, GEN8_PCU_);
+ IRQ_RESET(gt, GU_MISC_IRQ_OFFSET);
+ IRQ_RESET(gt, PCU_IRQ_OFFSET);
}
static void xe_irq_reset(struct xe_device *xe)
--
2.39.2
next prev parent reply other threads:[~2023-04-01 0:21 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-01 0:20 [Intel-xe] [PATCH v2 0/8] Interrupt cleanup and future-proofing Matt Roper
2023-04-01 0:20 ` [Intel-xe] [PATCH v2 1/8] drm/xe/irq: Drop gen3_ prefixes Matt Roper
2023-04-01 0:21 ` Matt Roper [this message]
2023-04-01 0:37 ` [Intel-xe] [PATCH v2 2/8] drm/xe/irq: Add helpers to find ISR/IIR/IMR/IER registers Lucas De Marchi
2023-04-01 0:21 ` [Intel-xe] [PATCH v2 3/8] drm/xe/irq: Drop IRQ_INIT and IRQ_RESET macros Matt Roper
2023-04-04 6:22 ` Lucas De Marchi
2023-04-01 0:21 ` [Intel-xe] [PATCH v2 4/8] drm/xe/irq: Drop unnecessary GEN11_ and GEN12_ register prefixes Matt Roper
2023-04-04 6:15 ` Lucas De Marchi
2023-04-01 0:21 ` [Intel-xe] [PATCH v2 5/8] drm/xe/irq: Rename and clarify top-level interrupt handling routines Matt Roper
2023-04-01 0:21 ` [Intel-xe] [PATCH v2 6/8] drm/xe/irq: Drop remaining "gen11_" prefix from IRQ functions Matt Roper
2023-04-01 0:21 ` [Intel-xe] [PATCH v2 7/8] drm/xe/irq: Drop commented-out code for non-existent media engines Matt Roper
2023-04-01 0:21 ` [Intel-xe] [PATCH v2 8/8] drm/xe/irq: Don't clobber display interrupts on multi-tile platforms Matt Roper
2023-04-01 0:34 ` [Intel-xe] ✓ CI.Patch_applied: success for Interrupt cleanup and future-proofing (rev2) Patchwork
2023-04-01 0:36 ` [Intel-xe] ✓ CI.KUnit: " Patchwork
2023-04-01 0:39 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-04-01 0:59 ` [Intel-xe] ○ CI.BAT: info " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230401002106.588656-3-matthew.d.roper@intel.com \
--to=matthew.d.roper@intel.com \
--cc=intel-xe@lists.freedesktop.org \
--cc=lucas.demarchi@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).