From: Thomas Garnier <thgarnie@chromium.org>
To: kernel-hardening@lists.openwall.com
Cc: kristen@linux.intel.com, Thomas Garnier <thgarnie@chromium.org>,
Juergen Gross <jgross@suse.com>,
Boris Ostrovsky <boris.ostrovsky@oracle.com>,
Stefano Stabellini <sstabellini@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
"H. Peter Anvin" <hpa@zytor.com>,
x86@kernel.org, Thomas Garnier <thgarnie@google.com>,
Ard Biesheuvel <ard.biesheuvel@linaro.org>,
Joerg Roedel <jroedel@suse.de>, "H.J. Lu" <hjl.tools@gmail.com>,
Jordan Borgner <mail@jordan-borgner.de>,
xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org
Subject: [PATCH v6 18/27] xen: Adapt assembly for PIE support
Date: Thu, 31 Jan 2019 11:24:25 -0800 [thread overview]
Message-ID: <20190131192533.34130-19-thgarnie@chromium.org> (raw)
In-Reply-To: <20190131192533.34130-1-thgarnie@chromium.org>
Change the assembly code to use the new _ASM_MOVABS macro which get a
symbol reference while being PIE compatible. Adapt the relocation tool
to ignore 32-bit Xen code.
Position Independent Executable (PIE) support will allow to extend the
KASLR randomization range below 0xffffffff80000000.
Signed-off-by: Thomas Garnier <thgarnie@chromium.org>
Reviewed-by: Juergen Gross <jgross@suse.com>
---
arch/x86/platform/pvh/head.S | 14 ++++++++++----
arch/x86/tools/relocs.c | 16 +++++++++++++++-
arch/x86/xen/xen-head.S | 11 ++++++-----
3 files changed, 31 insertions(+), 10 deletions(-)
diff --git a/arch/x86/platform/pvh/head.S b/arch/x86/platform/pvh/head.S
index 1f8825bbaffb..e52d8b31e01d 100644
--- a/arch/x86/platform/pvh/head.S
+++ b/arch/x86/platform/pvh/head.S
@@ -103,8 +103,8 @@ ENTRY(pvh_start_xen)
call xen_prepare_pvh
/* startup_64 expects boot_params in %rsi. */
- mov $_pa(pvh_bootparams), %rsi
- mov $_pa(startup_64), %rax
+ movabs $_pa(pvh_bootparams), %rsi
+ movabs $_pa(startup_64), %rax
jmp *%rax
#else /* CONFIG_X86_64 */
@@ -150,10 +150,16 @@ END(pvh_start_xen)
.section ".init.data","aw"
.balign 8
+ /*
+ * Use an ASM_PTR (quad on x64) for _pa(gdt_start) because PIE requires
+ * a pointer size storage value before applying the relocation. On
+ * 32-bit _ASM_PTR will be a long which is aligned the space needed for
+ * relocation.
+ */
gdt:
.word gdt_end - gdt_start
- .long _pa(gdt_start)
- .word 0
+ _ASM_PTR _pa(gdt_start)
+ .balign 8
gdt_start:
.quad 0x0000000000000000 /* NULL descriptor */
#ifdef CONFIG_X86_64
diff --git a/arch/x86/tools/relocs.c b/arch/x86/tools/relocs.c
index 2a3c703218cc..1b5ee38446b6 100644
--- a/arch/x86/tools/relocs.c
+++ b/arch/x86/tools/relocs.c
@@ -837,6 +837,16 @@ static int is_percpu_sym(ElfW(Sym) *sym, const char *symname)
strncmp(symname, "init_per_cpu_", 13);
}
+/*
+ * Check if the 32-bit relocation is within the xenpvh 32-bit code.
+ * If so, ignores it.
+ */
+static int is_in_xenpvh_assembly(Elf_Addr offset)
+{
+ Elf_Sym *sym = sym_lookup("pvh_start_xen");
+ return sym && (offset >= sym->st_value) &&
+ (offset < (sym->st_value + sym->st_size));
+}
static int do_reloc64(struct section *sec, Elf_Rel *rel, ElfW(Sym) *sym,
const char *symname)
@@ -909,8 +919,12 @@ static int do_reloc64(struct section *sec, Elf_Rel *rel, ElfW(Sym) *sym,
* the relocations are processed.
* Make sure that the offset will fit.
*/
- if (r_type != R_X86_64_64 && (int32_t)offset != (int64_t)offset)
+ if (r_type != R_X86_64_64 &&
+ (int32_t)offset != (int64_t)offset) {
+ if (is_in_xenpvh_assembly(offset))
+ break;
die("Relocation offset doesn't fit in 32 bits\n");
+ }
if (r_type == R_X86_64_64)
add_reloc(&relocs64, offset);
diff --git a/arch/x86/xen/xen-head.S b/arch/x86/xen/xen-head.S
index 5077ead5e59c..4418ff0a1d96 100644
--- a/arch/x86/xen/xen-head.S
+++ b/arch/x86/xen/xen-head.S
@@ -28,14 +28,15 @@ ENTRY(startup_xen)
/* Clear .bss */
xor %eax,%eax
- mov $__bss_start, %_ASM_DI
- mov $__bss_stop, %_ASM_CX
+ _ASM_MOVABS $__bss_start, %_ASM_DI
+ _ASM_MOVABS $__bss_stop, %_ASM_CX
sub %_ASM_DI, %_ASM_CX
shr $__ASM_SEL(2, 3), %_ASM_CX
rep __ASM_SIZE(stos)
- mov %_ASM_SI, xen_start_info
- mov $init_thread_union+THREAD_SIZE, %_ASM_SP
+ _ASM_MOVABS $xen_start_info, %_ASM_AX
+ _ASM_MOV %_ASM_SI, (%_ASM_AX)
+ _ASM_MOVABS $init_thread_union+THREAD_SIZE, %_ASM_SP
#ifdef CONFIG_X86_64
/* Set up %gs.
@@ -46,7 +47,7 @@ ENTRY(startup_xen)
* init data section till per cpu areas are set up.
*/
movl $MSR_GS_BASE,%ecx
- movq $INIT_PER_CPU_VAR(irq_stack_union),%rax
+ movabsq $INIT_PER_CPU_VAR(irq_stack_union),%rax
cdq
wrmsr
#endif
--
2.20.1.495.gaa96b0ce6b-goog
next prev parent reply other threads:[~2019-01-31 19:24 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-31 19:24 [PATCH v6 00/27] x86: PIE support and option to extend KASLR randomization Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 01/27] x86/crypto: Adapt assembly for PIE support Thomas Garnier
2019-02-07 11:48 ` Borislav Petkov
2019-02-07 17:01 ` Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 02/27] x86: Use symbol name in jump table " Thomas Garnier
2019-02-07 12:17 ` Borislav Petkov
2019-02-07 17:04 ` Thomas Garnier
2019-02-07 17:11 ` Borislav Petkov
2019-02-07 23:55 ` Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 03/27] x86: Add macro to get symbol address " Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 04/27] x86: relocate_kernel - Adapt assembly " Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 05/27] x86/entry/64: " Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 06/27] x86: pm-trace - " Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 07/27] x86/CPU: " Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 08/27] x86/acpi: " Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 09/27] x86/boot/64: " Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 10/27] x86/power/64: " Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 11/27] x86/paravirt: " Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 12/27] x86/alternatives: " Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 13/27] x86/boot/64: Build head64.c as mcmodel large when PIE is enabled Thomas Garnier
2019-02-01 11:15 ` Kirill A. Shutemov
2019-02-01 17:11 ` Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 14/27] x86/percpu: Adapt percpu for PIE support Thomas Garnier
2019-01-31 20:57 ` Christopher Lameter
2019-01-31 22:49 ` Thomas Garnier
2019-02-01 2:31 ` Christopher Lameter
2019-02-01 17:13 ` Thomas Garnier
2019-04-08 15:58 ` Thomas Garnier
2019-04-08 17:56 ` Christopher Lameter
2019-04-08 18:08 ` Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 15/27] compiler: Option to default to hidden symbols Thomas Garnier
2019-02-01 7:12 ` Dan Carpenter
2019-02-01 17:00 ` Thomas Garnier
2019-02-01 8:22 ` Adrian Hunter
2019-02-01 17:35 ` Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 16/27] compiler: Option to add PROVIDE_HIDDEN replacement for weak symbols Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 17/27] x86/relocs: Handle PIE relocations Thomas Garnier
2019-01-31 19:24 ` Thomas Garnier [this message]
2019-01-31 19:24 ` [PATCH v6 19/27] kvm: Adapt assembly for PIE support Thomas Garnier
2019-02-06 19:56 ` Sean Christopherson
2019-02-06 21:23 ` Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 20/27] x86: Support global stack cookie Thomas Garnier
2019-02-01 19:27 ` Andy Lutomirski
2019-02-01 20:21 ` Thomas Garnier
2019-02-01 22:36 ` Andy Lutomirski
2019-02-01 23:56 ` Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 21/27] x86/ftrace: Adapt function tracing for PIE support Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 22/27] x86/modules: Add option to start module section after kernel Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 23/27] x86/modules: Adapt module loading for PIE support Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 24/27] x86/mm: Make the x86 GOT read-only Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 25/27] x86/pie: Add option to build the kernel as PIE Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 26/27] x86/relocs: Add option to generate 64-bit relocations Thomas Garnier
2019-01-31 19:24 ` [PATCH v6 27/27] x86/kaslr: Add option to extend KASLR range from 1GB to 3GB Thomas Garnier
2019-01-31 19:59 ` [PATCH v6 00/27] x86: PIE support and option to extend KASLR randomization Kees Cook
2019-01-31 21:40 ` Konrad Rzeszutek Wilk
2019-01-31 22:42 ` Thomas Garnier
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