From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F9ECC38A2A for ; Thu, 7 May 2020 13:43:24 +0000 (UTC) Received: from mother.openwall.net (mother.openwall.net [195.42.179.200]) by mail.kernel.org (Postfix) with SMTP id 9A6572075E for ; Thu, 7 May 2020 13:43:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9A6572075E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kernel-hardening-return-18738-kernel-hardening=archiver.kernel.org@lists.openwall.com Received: (qmail 3191 invoked by uid 550); 7 May 2020 13:43:16 -0000 Mailing-List: contact kernel-hardening-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Received: (qmail 3157 invoked from network); 7 May 2020 13:43:15 -0000 Date: Thu, 7 May 2020 14:43:00 +0100 From: Catalin Marinas To: Will Deacon Cc: Ard Biesheuvel , Linux ARM , kernel-hardening@lists.openwall.com, Mark Rutland Subject: Re: [RFC PATCH] arm64: remove CONFIG_DEBUG_ALIGN_RODATA feature Message-ID: <20200507134259.GA3180@gaia> References: <20200329141258.31172-1-ardb@kernel.org> <20200330135121.GD10633@willie-the-truck> <20200330140441.GE10633@willie-the-truck> <20200330142805.GA11312@willie-the-truck> <20200402113033.GD21087@mbp> <20200505104404.GB19710@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200505104404.GB19710@willie-the-truck> User-Agent: Mutt/1.10.1 (2018-07-13) On Tue, May 05, 2020 at 11:44:06AM +0100, Will Deacon wrote: > Catalin -- did you get anything back from the architects about the cache > hit behaviour? Any read from a non-cacheable alias would be coherent with writes using the same non-cacheable attributes, irrespective of other cacheable aliases (of course, subject to the cache lines having been previously cleaned/invalidated to avoid dirty lines evictions). So as long as the hardware works as per the ARM ARM (B2.8), we don't need to unmap the non-cacheable DMA buffers from the linear map. -- Catalin