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From: Luca Ceresoli <luca@lucaceresoli.net>
To: Greg KH <greg@kroah.com>
Cc: "Valdis Klētnieks" <valdis.kletnieks@vt.edu>,
	kernelnewbies@kernelnewbies.org
Subject: Re: Remote I/O bus
Date: Mon, 7 Oct 2019 09:48:46 +0200
Message-ID: <5f7edff6-e8c2-1e3d-f552-9e68e3474c31@lucaceresoli.net> (raw)
In-Reply-To: <20191006091828.GA2746237@kroah.com>

Hi Greg,

On 06/10/19 11:18, Greg KH wrote:
> On Sun, Oct 06, 2019 at 12:29:18AM +0200, Luca Ceresoli wrote:
>> BTW I guess having an FPGA external to the SoC connected via SPI or I2C
>> is not uncommon. Am I wrong?
> 
> Not uncommon at all, look at the drivers/fpga/ subsystem for a standard
> way to access those types of chips with a standard api.

My question was probably ambiguously stated, sorry.

drivers/fpga/ has drivers to send a bitstream to an unconfigured FPGA,
which uses protocols casted in silicon by FPGA vendors.

My question was about the connection between a configured FPGA and the
main SoC. This is subject to the fantasy of the FPGA implementer, which
explains why there is no specific protocol implemented in mainline: it
is usually either a standard bus (typically memory-mapped or PCIe) or a
custom protocol over I2C or SPI.

I think only DFL is somewhat different, but it doesn't apply to my case
since it assumes MMIO, and if I had MMIO I wouldn't have started this
thread at all.

-- 
Luca

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Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-04 11:04 Luca Ceresoli
2019-10-04 13:22 ` Greg KH
2019-10-04 14:08   ` Luca Ceresoli
2019-10-04 14:54     ` Greg KH
2019-10-04 15:08       ` Luca Ceresoli
2019-10-04 21:51         ` Valdis Klētnieks
2019-10-05 22:29           ` Luca Ceresoli
2019-10-06  0:19             ` Valdis Klētnieks
2019-10-06  9:18             ` Greg KH
2019-10-07  7:48               ` Luca Ceresoli [this message]

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