Kernel Newbies archive on lore.kernel.org
 help / color / Atom feed
From: Muni Sekhar <munisekharrms@gmail.com>
To: Onur Atilla <onurati@posteo.de>
Cc: kernelnewbies <kernelnewbies@kernelnewbies.org>, primoz.beltram@kate.si
Subject: Re: read the memory mapped address - pcie - kernel hangs
Date: Sat, 11 Jan 2020 08:43:09 +0530
Message-ID: <CAHhAz+huy5m4V+V99HMeU+4SB+vihWH-Af==gw5RtoRuuWfY0Q@mail.gmail.com> (raw)
In-Reply-To: <fed5e64a-ec0d-563b-f9ca-e6266fb4aad4@posteo.de>

[-- Attachment #1.1: Type: text/plain, Size: 2033 bytes --]

Thanks, I'll check it out.

On Sat, 11 Jan, 2020, 4:33 AM Onur Atilla, <onurati@posteo.de> wrote:

> On 10.01.20 15:58, Muni Sekhar wrote:
> > On Fri, Jan 10, 2020 at 4:46 PM Primoz Beltram <primoz.beltram@kate.si>
> wrote:
> >>
> >> Hi,
> >> Have read also other replays to this topic.
> >> I have seen-debug such deadlock problems with FPGA based PCIe endpoint
> >> devices (Xilinx chips) and usually (if not signal integrity problems),
> >> the problem was in wrong AXI master/slave bus handling in FPGA design.
> >> I guess you have FPGA Xilinx PCIe endpoint IP core attached as AXI
> >> master to FPGA internal AXI bus (access to AXI slaves inside FPGA
> design).
> >> If FPGA code in your design does not handle correctly AXI master
> >> read/write requests, e.g. FPGA AXI slave does not generate bus ACK in
> >> correct way, the PCIe bus will stay locked (no PCIe completion sent
> >> back), resulting in complete system lock. Some PCIe root chips have
> >> diagnostic LEDs to help decode PCIe problems.
> >>  From your notice about doing two 32bit reads on 64bit CPU, I would
> >> guess the problem is in handling AXI transfer size signals in FPGA slave
> >> code.
> >> I would suggest you to check the code in FPGA design. You can use FPGA
> >> test bench simulation to check the behaviour of PCIe endpoint originated
> >> AXI read/write requests.
> >> Xilinx provides test bench simulation code for their PCIe IP's.
> >> They provide also PCIe root port model, so you can simulate AXI
> >> read/writes accesses as they would come from CPU I/O memory requests via
> >> PCIe TLPs.
> > Thank you so much for sharing valuable information, will work on this.
> >
> >> WBR Primoz
>
> Hi,
>
> you may also want to have a look at the AXI Timeout Block (ATB) to
> prevent system/core locks due to a missing ACK of a slave. If given by
> the HW, ATB generates an alternative response in case the slave fails to
> respond within a given time. It may also trigger an interrupt to help
> handle/debug the error.
>
> Regards,
> Onur
>
>

[-- Attachment #1.2: Type: text/html, Size: 2658 bytes --]

<div dir="auto">Thanks, I&#39;ll check it out. </div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Sat, 11 Jan, 2020, 4:33 AM Onur Atilla, &lt;<a href="mailto:onurati@posteo.de">onurati@posteo.de</a>&gt; wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">On 10.01.20 15:58, Muni Sekhar wrote:<br>
&gt; On Fri, Jan 10, 2020 at 4:46 PM Primoz Beltram &lt;<a href="mailto:primoz.beltram@kate.si" target="_blank" rel="noreferrer">primoz.beltram@kate.si</a>&gt; wrote:<br>
&gt;&gt;<br>
&gt;&gt; Hi,<br>
&gt;&gt; Have read also other replays to this topic.<br>
&gt;&gt; I have seen-debug such deadlock problems with FPGA based PCIe endpoint<br>
&gt;&gt; devices (Xilinx chips) and usually (if not signal integrity problems),<br>
&gt;&gt; the problem was in wrong AXI master/slave bus handling in FPGA design.<br>
&gt;&gt; I guess you have FPGA Xilinx PCIe endpoint IP core attached as AXI<br>
&gt;&gt; master to FPGA internal AXI bus (access to AXI slaves inside FPGA design).<br>
&gt;&gt; If FPGA code in your design does not handle correctly AXI master<br>
&gt;&gt; read/write requests, e.g. FPGA AXI slave does not generate bus ACK in<br>
&gt;&gt; correct way, the PCIe bus will stay locked (no PCIe completion sent<br>
&gt;&gt; back), resulting in complete system lock. Some PCIe root chips have<br>
&gt;&gt; diagnostic LEDs to help decode PCIe problems.<br>
&gt;&gt;  From your notice about doing two 32bit reads on 64bit CPU, I would<br>
&gt;&gt; guess the problem is in handling AXI transfer size signals in FPGA slave<br>
&gt;&gt; code.<br>
&gt;&gt; I would suggest you to check the code in FPGA design. You can use FPGA<br>
&gt;&gt; test bench simulation to check the behaviour of PCIe endpoint originated<br>
&gt;&gt; AXI read/write requests.<br>
&gt;&gt; Xilinx provides test bench simulation code for their PCIe IP&#39;s.<br>
&gt;&gt; They provide also PCIe root port model, so you can simulate AXI<br>
&gt;&gt; read/writes accesses as they would come from CPU I/O memory requests via<br>
&gt;&gt; PCIe TLPs.<br>
&gt; Thank you so much for sharing valuable information, will work on this.<br>
&gt; <br>
&gt;&gt; WBR Primoz<br>
<br>
Hi,<br>
<br>
you may also want to have a look at the AXI Timeout Block (ATB) to<br>
prevent system/core locks due to a missing ACK of a slave. If given by<br>
the HW, ATB generates an alternative response in case the slave fails to<br>
respond within a given time. It may also trigger an interrupt to help<br>
handle/debug the error.<br>
<br>
Regards,<br>
Onur<br>
<br>
</blockquote></div>

[-- Attachment #2: Type: text/plain, Size: 170 bytes --]

_______________________________________________
Kernelnewbies mailing list
Kernelnewbies@kernelnewbies.org
https://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies

      reply index

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-08 19:00 Muni Sekhar
2020-01-08 19:45 ` Greg KH
2020-01-09 11:14   ` Muni Sekhar
2020-01-09 11:37     ` Greg KH
2020-01-09 12:20       ` Muni Sekhar
2020-01-09 18:12         ` Greg KH
2020-01-10 11:15 ` Primoz Beltram
2020-01-10 14:58   ` Muni Sekhar
2020-01-10 23:03     ` Onur Atilla
2020-01-11  3:13       ` Muni Sekhar [this message]

Reply instructions:

You may reply publically to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to='CAHhAz+huy5m4V+V99HMeU+4SB+vihWH-Af==gw5RtoRuuWfY0Q@mail.gmail.com' \
    --to=munisekharrms@gmail.com \
    --cc=kernelnewbies@kernelnewbies.org \
    --cc=onurati@posteo.de \
    --cc=primoz.beltram@kate.si \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

Kernel Newbies archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/kernelnewbies/0 kernelnewbies/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 kernelnewbies kernelnewbies/ https://lore.kernel.org/kernelnewbies \
		kernelnewbies@kernelnewbies.org
	public-inbox-index kernelnewbies

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernelnewbies.kernelnewbies


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git