From: Auger Eric <eric.auger@redhat.com>
To: Marc Zyngier <maz@kernel.org>,
linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Jason Cooper <jason@lakedaemon.net>,
Robert Richter <rrichter@marvell.com>,
Thomas Gleixner <tglx@linutronix.de>,
Zenghui Yu <yuzenghui@huawei.com>,
James Morse <james.morse@arm.com>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: Re: [PATCH v5 18/23] KVM: arm64: GICv4.1: Add direct injection capability to SGI registers
Date: Fri, 20 Mar 2020 09:11:38 +0100 [thread overview]
Message-ID: <06705d70-0f99-e719-af52-1a5f778562d8@redhat.com> (raw)
In-Reply-To: <20200304203330.4967-19-maz@kernel.org>
Hi Marc,
On 3/4/20 9:33 PM, Marc Zyngier wrote:
> Most of the GICv3 emulation code that deals with SGIs now has to be
> aware of the v4.1 capabilities in order to benefit from it.
>
> Add such support, keyed on the interrupt having the hw flag set and
> being a SGI.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> virt/kvm/arm/vgic/vgic-mmio-v3.c | 15 +++++-
> virt/kvm/arm/vgic/vgic-mmio.c | 88 ++++++++++++++++++++++++++++++--
> 2 files changed, 96 insertions(+), 7 deletions(-)
>
> diff --git a/virt/kvm/arm/vgic/vgic-mmio-v3.c b/virt/kvm/arm/vgic/vgic-mmio-v3.c
> index ebc218840fc2..de89da76a379 100644
> --- a/virt/kvm/arm/vgic/vgic-mmio-v3.c
> +++ b/virt/kvm/arm/vgic/vgic-mmio-v3.c
> @@ -6,6 +6,7 @@
> #include <linux/irqchip/arm-gic-v3.h>
> #include <linux/kvm.h>
> #include <linux/kvm_host.h>
> +#include <linux/interrupt.h>
> #include <kvm/iodev.h>
> #include <kvm/arm_vgic.h>
>
> @@ -942,8 +943,18 @@ void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1)
> * generate interrupts of either group.
> */
> if (!irq->group || allow_group1) {
> - irq->pending_latch = true;
> - vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
> + if (!irq->hw) {
> + irq->pending_latch = true;
> + vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
> + } else {
> + /* HW SGI? Ask the GIC to inject it */
> + int err;
nit: add line
> + err = irq_set_irqchip_state(irq->host_irq,
> + IRQCHIP_STATE_PENDING,
> + true);
> + WARN_RATELIMIT(err, "IRQ %d", irq->host_irq);
> + raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
> + }
> } else {
> raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
> }
> diff --git a/virt/kvm/arm/vgic/vgic-mmio.c b/virt/kvm/arm/vgic/vgic-mmio.c
> index 97fb2a40e6ba..2199302597fa 100644
> --- a/virt/kvm/arm/vgic/vgic-mmio.c
> +++ b/virt/kvm/arm/vgic/vgic-mmio.c
> @@ -5,6 +5,8 @@
>
> #include <linux/bitops.h>
> #include <linux/bsearch.h>
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> #include <linux/kvm.h>
> #include <linux/kvm_host.h>
> #include <kvm/iodev.h>
> @@ -59,6 +61,11 @@ unsigned long vgic_mmio_read_group(struct kvm_vcpu *vcpu,
> return value;
> }
>
> +static void vgic_update_vsgi(struct vgic_irq *irq)
> +{
> + WARN_ON(its_prop_update_vsgi(irq->host_irq, irq->priority, irq->group));
> +}
> +
> void vgic_mmio_write_group(struct kvm_vcpu *vcpu, gpa_t addr,
> unsigned int len, unsigned long val)
> {
> @@ -71,7 +78,12 @@ void vgic_mmio_write_group(struct kvm_vcpu *vcpu, gpa_t addr,
>
> raw_spin_lock_irqsave(&irq->irq_lock, flags);
> irq->group = !!(val & BIT(i));
> - vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
> + if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
> + vgic_update_vsgi(irq);
> + raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
> + } else {
> + vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
> + }
>
> vgic_put_irq(vcpu->kvm, irq);
> }
> @@ -113,7 +125,21 @@ void vgic_mmio_write_senable(struct kvm_vcpu *vcpu,
> struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
>
> raw_spin_lock_irqsave(&irq->irq_lock, flags);
> - if (vgic_irq_is_mapped_level(irq)) {
> + if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
> + if (!irq->enabled) {
> + struct irq_data *data;
> +
> + irq->enabled = true;
> + data = &irq_to_desc(irq->host_irq)->irq_data;
> + while (irqd_irq_disabled(data))
> + enable_irq(irq->host_irq);
could you explain me why the while() is requested?
> + }
> +
> + raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
> + vgic_put_irq(vcpu->kvm, irq);
> +
> + continue;
> + } else if (vgic_irq_is_mapped_level(irq)) {
> bool was_high = irq->line_level;
>
> /*
> @@ -148,6 +174,8 @@ void vgic_mmio_write_cenable(struct kvm_vcpu *vcpu,
> struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
>
> raw_spin_lock_irqsave(&irq->irq_lock, flags);
> + if (irq->hw && vgic_irq_is_sgi(irq->intid) && irq->enabled)
> + disable_irq_nosync(irq->host_irq);
>
> irq->enabled = false;
>
> @@ -167,10 +195,22 @@ unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
> for (i = 0; i < len * 8; i++) {
> struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
> unsigned long flags;
> + bool val;
>
> raw_spin_lock_irqsave(&irq->irq_lock, flags);
> - if (irq_is_pending(irq))
> - value |= (1U << i);
> + if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
> + int err;
> +
> + val = false;
> + err = irq_get_irqchip_state(irq->host_irq,
> + IRQCHIP_STATE_PENDING,
> + &val);
> + WARN_RATELIMIT(err, "IRQ %d", irq->host_irq);
> + } else {
> + val = irq_is_pending(irq);
> + }
> +
> + value |= ((u32)val << i);
> raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
>
> vgic_put_irq(vcpu->kvm, irq);
> @@ -215,6 +255,21 @@ void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,
> }
>
> raw_spin_lock_irqsave(&irq->irq_lock, flags);
> +
> + if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
> + /* HW SGI? Ask the GIC to inject it */
> + int err;
nit: extra line
> + err = irq_set_irqchip_state(irq->host_irq,
> + IRQCHIP_STATE_PENDING,
> + true);
> + WARN_RATELIMIT(err, "IRQ %d", irq->host_irq);
> +
> + raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
> + vgic_put_irq(vcpu->kvm, irq);
> +
> + continue;
> + }
> +
> if (irq->hw)
> vgic_hw_irq_spending(vcpu, irq, is_uaccess);
> else
> @@ -269,6 +324,20 @@ void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu,
>
> raw_spin_lock_irqsave(&irq->irq_lock, flags);
>
> + if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
> + /* HW SGI? Ask the GIC to clear its pending bit */
> + int err;
> + err = irq_set_irqchip_state(irq->host_irq,
> + IRQCHIP_STATE_PENDING,
> + false);
> + WARN_RATELIMIT(err, "IRQ %d", irq->host_irq);
> +
> + raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
> + vgic_put_irq(vcpu->kvm, irq);
> +
> + continue;
> + }
> +
> if (irq->hw)
> vgic_hw_irq_cpending(vcpu, irq, is_uaccess);
> else
> @@ -318,8 +387,15 @@ static void vgic_mmio_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
>
> raw_spin_lock_irqsave(&irq->irq_lock, flags);
>
> - if (irq->hw) {
> + if (irq->hw && !vgic_irq_is_sgi(irq->intid)) {
> vgic_hw_irq_change_active(vcpu, irq, active, !requester_vcpu);
> + } else if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
> + /*
> + * GICv4.1 VSGI feature doesn't track an active state,
> + * so let's not kid ourselves, there is nothing we can
> + * do here.
> + */
> + irq->active = false;
> } else {
> u32 model = vcpu->kvm->arch.vgic.vgic_model;
> u8 active_source;
> @@ -493,6 +569,8 @@ void vgic_mmio_write_priority(struct kvm_vcpu *vcpu,
> raw_spin_lock_irqsave(&irq->irq_lock, flags);
> /* Narrow the priority range to what we actually support */
> irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS);
> + if (irq->hw && vgic_irq_is_sgi(irq->intid))
> + vgic_update_vsgi(irq);
> raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
>
> vgic_put_irq(vcpu->kvm, irq);
>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Thanks
Eric
next prev parent reply other threads:[~2020-03-20 8:11 UTC|newest]
Thread overview: 99+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-04 20:33 [PATCH v5 00/23] irqchip/gic-v4: GICv4.1 architecture support Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 01/23] irqchip/gic-v3: Use SGIs without active state if offered Marc Zyngier
2020-03-12 6:30 ` Zenghui Yu
2020-03-12 9:28 ` Marc Zyngier
2020-03-12 12:05 ` Marc Zyngier
2020-03-13 1:39 ` Zenghui Yu
2020-03-12 17:16 ` Auger Eric
2020-03-12 17:23 ` Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 02/23] irqchip/gic-v4.1: Skip absent CPUs while iterating over redistributors Marc Zyngier
2020-03-16 17:10 ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 03/23] irqchip/gic-v4.1: Ensure mutual exclusion between vPE affinity change and RD access Marc Zyngier
2020-03-12 6:56 ` Zenghui Yu
2020-03-04 20:33 ` [PATCH v5 04/23] irqchip/gic-v4.1: Wait for completion of redistributor's INVALL operation Marc Zyngier
2020-03-20 14:23 ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 05/23] irqchip/gic-v4.1: Ensure mutual exclusion betwen invalidations on the same RD Marc Zyngier
2020-03-12 7:11 ` Zenghui Yu
2020-03-20 14:23 ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 06/23] irqchip/gic-v4.1: Advertise support v4.1 to KVM Marc Zyngier
2020-03-16 17:10 ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 07/23] irqchip/gic-v4.1: Map the ITS SGIR register page Marc Zyngier
2020-03-16 17:10 ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 08/23] irqchip/gic-v4.1: Plumb skeletal VSGI irqchip Marc Zyngier
2020-03-16 17:10 ` Auger Eric
2020-03-19 10:03 ` Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 09/23] irqchip/gic-v4.1: Add initial SGI configuration Marc Zyngier
2020-03-16 17:53 ` Auger Eric
2020-03-17 2:02 ` Zenghui Yu
2020-03-17 8:36 ` Auger Eric
2020-03-19 10:20 ` Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 10/23] irqchip/gic-v4.1: Plumb mask/unmask SGI callbacks Marc Zyngier
2020-03-16 18:15 ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 11/23] irqchip/gic-v4.1: Plumb get/set_irqchip_state " Marc Zyngier
2020-03-12 7:41 ` Zenghui Yu
2020-03-16 21:43 ` Auger Eric
2020-03-19 10:27 ` Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 12/23] irqchip/gic-v4.1: Plumb set_vcpu_affinity " Marc Zyngier
2020-03-17 10:35 ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 13/23] irqchip/gic-v4.1: Move doorbell management to the GICv4 abstraction layer Marc Zyngier
2020-03-12 8:20 ` Zenghui Yu
2020-03-04 20:33 ` [PATCH v5 14/23] irqchip/gic-v4.1: Add VSGI allocation/teardown Marc Zyngier
2020-03-12 8:06 ` Zenghui Yu
2020-03-04 20:33 ` [PATCH v5 15/23] irqchip/gic-v4.1: Add VSGI property setup Marc Zyngier
2020-03-12 8:09 ` Zenghui Yu
2020-03-17 10:30 ` Auger Eric
2020-03-19 10:57 ` Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 16/23] irqchip/gic-v4.1: Eagerly vmap vPEs Marc Zyngier
2020-03-12 8:12 ` Zenghui Yu
2020-03-17 2:49 ` Zenghui Yu
2020-03-19 10:55 ` Marc Zyngier
2020-03-20 2:31 ` Zenghui Yu
2020-03-04 20:33 ` [PATCH v5 17/23] KVM: arm64: GICv4.1: Let doorbells be auto-enabled Marc Zyngier
2020-03-12 8:15 ` Zenghui Yu
2020-03-17 11:04 ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 18/23] KVM: arm64: GICv4.1: Add direct injection capability to SGI registers Marc Zyngier
2020-03-18 3:28 ` Zenghui Yu
2020-03-20 8:11 ` Auger Eric [this message]
2020-03-20 10:05 ` Marc Zyngier
2020-03-20 10:56 ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 19/23] KVM: arm64: GICv4.1: Allow SGIs to switch between HW and SW interrupts Marc Zyngier
2020-03-19 16:16 ` Auger Eric
2020-03-19 19:52 ` Marc Zyngier
2020-03-19 20:13 ` Auger Eric
2020-03-20 9:17 ` Marc Zyngier
2020-03-20 4:22 ` Zenghui Yu
2020-03-04 20:33 ` [PATCH v5 20/23] KVM: arm64: GICv4.1: Plumb SGI implementation selection in the distributor Marc Zyngier
2020-03-18 6:34 ` Zenghui Yu
2020-03-19 12:10 ` Marc Zyngier
2020-03-19 20:38 ` Auger Eric
2020-03-20 3:08 ` Zenghui Yu
2020-03-20 7:59 ` Auger Eric
2020-03-20 9:46 ` Marc Zyngier
2020-03-20 11:09 ` Auger Eric
2020-03-20 11:20 ` Marc Zyngier
2020-03-20 3:53 ` Zenghui Yu
2020-03-20 9:01 ` Marc Zyngier
2020-03-23 8:11 ` Zenghui Yu
2020-03-23 8:25 ` Marc Zyngier
2020-03-23 12:40 ` Zenghui Yu
2020-03-04 20:33 ` [PATCH v5 21/23] KVM: arm64: GICv4.1: Reload VLPI configuration on distributor enable/disable Marc Zyngier
2020-03-18 3:17 ` Zenghui Yu
2020-03-19 12:18 ` Marc Zyngier
2020-03-04 20:33 ` [PATCH v5 22/23] KVM: arm64: GICv4.1: Allow non-trapping WFI when using HW SGIs Marc Zyngier
2020-03-20 4:23 ` Zenghui Yu
2020-03-20 8:12 ` Auger Eric
2020-03-04 20:33 ` [PATCH v5 23/23] KVM: arm64: GICv4.1: Expose HW-based SGIs in debugfs Marc Zyngier
2020-03-18 3:19 ` Zenghui Yu
2020-03-19 15:05 ` Auger Eric
2020-03-19 15:21 ` Marc Zyngier
2020-03-19 15:43 ` Auger Eric
2020-03-19 16:16 ` Marc Zyngier
2020-03-19 16:17 ` Auger Eric
2020-03-20 4:38 ` Zenghui Yu
2020-03-20 9:09 ` Marc Zyngier
2020-03-20 11:35 ` Zenghui Yu
2020-03-20 11:46 ` Marc Zyngier
2020-03-20 12:09 ` Zenghui Yu
2020-03-05 3:39 ` [PATCH v5 00/23] irqchip/gic-v4: GICv4.1 architecture support Zenghui Yu
2020-03-09 8:17 ` Zenghui Yu
2020-03-09 8:46 ` Marc Zyngier
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