From: kajoljain <kjain@linux.ibm.com>
To: Athira Rajeev <atrajeev@linux.vnet.ibm.com>,
mpe@ellerman.id.au, acme@kernel.org, jolsa@kernel.org
Cc: ego@linux.vnet.ibm.com, mikey@neuling.org,
maddy@linux.vnet.ibm.com, kvm@vger.kernel.org,
kvm-ppc@vger.kernel.org, svaidyan@in.ibm.com,
linuxppc-dev@lists.ozlabs.org
Subject: Re: [v3 15/15] tools/perf: Add perf tools support for extended regs in power10
Date: Tue, 21 Jul 2020 11:34:37 +0530 [thread overview]
Message-ID: <0ea080de-8847-c4dd-dcb8-dd9d85529630@linux.ibm.com> (raw)
In-Reply-To: <1594996707-3727-16-git-send-email-atrajeev@linux.vnet.ibm.com>
On 7/17/20 8:08 PM, Athira Rajeev wrote:
> Added support for supported regs which are new in power10
> ( MMCR3, SIER2, SIER3 ) to sample_reg_mask in the tool side
> to use with `-I?` option. Also added PVR check to send extended
> mask for power10 at kernel while capturing extended regs in
> each sample.
>
> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
> ---
> tools/arch/powerpc/include/uapi/asm/perf_regs.h | 6 ++++++
> tools/perf/arch/powerpc/include/perf_regs.h | 3 +++
> tools/perf/arch/powerpc/util/perf_regs.c | 6 ++++++
> 3 files changed, 15 insertions(+)
>
Reviewed-by: Kajol Jain <kjain@linux.ibm.com>
Thanks,
Kajol Jain
> diff --git a/tools/arch/powerpc/include/uapi/asm/perf_regs.h b/tools/arch/powerpc/include/uapi/asm/perf_regs.h
> index 225c64c..bdf5f10 100644
> --- a/tools/arch/powerpc/include/uapi/asm/perf_regs.h
> +++ b/tools/arch/powerpc/include/uapi/asm/perf_regs.h
> @@ -52,6 +52,9 @@ enum perf_event_powerpc_regs {
> PERF_REG_POWERPC_MMCR0,
> PERF_REG_POWERPC_MMCR1,
> PERF_REG_POWERPC_MMCR2,
> + PERF_REG_POWERPC_MMCR3,
> + PERF_REG_POWERPC_SIER2,
> + PERF_REG_POWERPC_SIER3,
> /* Max regs without the extended regs */
> PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1,
> };
> @@ -60,6 +63,9 @@ enum perf_event_powerpc_regs {
>
> /* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300 */
> #define PERF_REG_PMU_MASK_300 (((1ULL << (PERF_REG_POWERPC_MMCR2 + 1)) - 1) - PERF_REG_PMU_MASK)
> +/* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31 */
> +#define PERF_REG_PMU_MASK_31 (((1ULL << (PERF_REG_POWERPC_SIER3 + 1)) - 1) - PERF_REG_PMU_MASK)
>
> #define PERF_REG_MAX_ISA_300 (PERF_REG_POWERPC_MMCR2 + 1)
> +#define PERF_REG_MAX_ISA_31 (PERF_REG_POWERPC_SIER3 + 1)
> #endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */
> diff --git a/tools/perf/arch/powerpc/include/perf_regs.h b/tools/perf/arch/powerpc/include/perf_regs.h
> index 46ed00d..63f3ac9 100644
> --- a/tools/perf/arch/powerpc/include/perf_regs.h
> +++ b/tools/perf/arch/powerpc/include/perf_regs.h
> @@ -68,6 +68,9 @@
> [PERF_REG_POWERPC_MMCR0] = "mmcr0",
> [PERF_REG_POWERPC_MMCR1] = "mmcr1",
> [PERF_REG_POWERPC_MMCR2] = "mmcr2",
> + [PERF_REG_POWERPC_MMCR3] = "mmcr3",
> + [PERF_REG_POWERPC_SIER2] = "sier2",
> + [PERF_REG_POWERPC_SIER3] = "sier3",
> };
>
> static inline const char *perf_reg_name(int id)
> diff --git a/tools/perf/arch/powerpc/util/perf_regs.c b/tools/perf/arch/powerpc/util/perf_regs.c
> index d64ba0c..2b6d470 100644
> --- a/tools/perf/arch/powerpc/util/perf_regs.c
> +++ b/tools/perf/arch/powerpc/util/perf_regs.c
> @@ -14,6 +14,7 @@
> #include <linux/kernel.h>
>
> #define PVR_POWER9 0x004E
> +#define PVR_POWER10 0x0080
>
> const struct sample_reg sample_reg_masks[] = {
> SMPL_REG(r0, PERF_REG_POWERPC_R0),
> @@ -64,6 +65,9 @@
> SMPL_REG(mmcr0, PERF_REG_POWERPC_MMCR0),
> SMPL_REG(mmcr1, PERF_REG_POWERPC_MMCR1),
> SMPL_REG(mmcr2, PERF_REG_POWERPC_MMCR2),
> + SMPL_REG(mmcr3, PERF_REG_POWERPC_MMCR3),
> + SMPL_REG(sier2, PERF_REG_POWERPC_SIER2),
> + SMPL_REG(sier3, PERF_REG_POWERPC_SIER3),
> SMPL_REG_END
> };
>
> @@ -194,6 +198,8 @@ uint64_t arch__intr_reg_mask(void)
> version = (((mfspr(SPRN_PVR)) >> 16) & 0xFFFF);
> if (version == PVR_POWER9)
> extended_mask = PERF_REG_PMU_MASK_300;
> + else if (version == PVR_POWER10)
> + extended_mask = PERF_REG_PMU_MASK_31;
> else
> return mask;
>
>
next prev parent reply other threads:[~2020-07-21 6:04 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-17 14:38 [v3 00/15] powerpc/perf: Add support for power10 PMU Hardware Athira Rajeev
2020-07-17 14:38 ` [v3 01/15] powerpc/perf: Update cpu_hw_event to use `struct` for storing MMCR registers Athira Rajeev
2020-07-21 3:42 ` Jordan Niethe
2020-07-17 14:38 ` [v3 02/15] KVM: PPC: Book3S HV: Cleanup updates for kvm vcpu MMCR Athira Rajeev
2020-07-21 3:54 ` Paul Mackerras
2020-07-22 4:38 ` Michael Ellerman
[not found] ` <B83C440A-1AC4-4737-8AB1-EB9A6B8A474B@linux.vnet.ibm.com>
2020-07-22 4:37 ` Michael Ellerman
2020-07-22 4:54 ` Paul Mackerras
2020-07-22 6:03 ` Madhavan Srinivasan
2020-07-17 14:38 ` [v3 03/15] powerpc/perf: Update Power PMU cache_events to u64 type Athira Rajeev
2020-07-17 14:38 ` [v3 04/15] powerpc/perf: Add support for ISA3.1 PMU SPRs Athira Rajeev
2020-07-22 4:18 ` Jordan Niethe
[not found] ` <F54F7D50-8255-428A-B79E-EE1E2D70074B@linux.vnet.ibm.com>
2020-07-22 10:52 ` Jordan Niethe
2020-07-22 12:03 ` Michael Ellerman
2020-07-17 14:38 ` [v3 05/15] KVM: PPC: Book3S HV: Save/restore new PMU registers Athira Rajeev
2020-07-17 14:38 ` [v3 06/15] powerpc/xmon: Add PowerISA v3.1 PMU SPRs Athira Rajeev
2020-07-17 14:38 ` [v3 07/15] powerpc/perf: Add power10_feat to dt_cpu_ftrs Athira Rajeev
2020-07-22 4:41 ` Jordan Niethe
[not found] ` <9A4E06A2-5686-4C85-B2F7-0904F195B58A@linux.vnet.ibm.com>
2020-07-22 10:39 ` Michael Ellerman
2020-07-22 10:49 ` Jordan Niethe
2020-07-17 14:38 ` [v3 08/15] powerpc/perf: power10 Performance Monitoring support Athira Rajeev
2020-07-17 14:38 ` [v3 09/15] powerpc/perf: Ignore the BHRB kernel address filtering for P10 Athira Rajeev
2020-07-17 14:38 ` [v3 10/15] powerpc/perf: Add Power10 BHRB filter support for PERF_SAMPLE_BRANCH_IND_CALL/COND Athira Rajeev
2020-07-17 14:38 ` [v3 11/15] powerpc/perf: BHRB control to disable BHRB logic when not used Athira Rajeev
2020-07-20 10:05 ` Gautham R Shenoy
2020-07-23 1:26 ` Jordan Niethe
2020-07-23 1:28 ` Jordan Niethe
2020-07-17 14:38 ` [v3 12/15] powerpc/perf: Add support for outputting extended regs in perf intr_regs Athira Rajeev
2020-07-19 11:17 ` kernel test robot
2020-07-21 6:02 ` kajoljain
2020-07-23 5:44 ` kajoljain
2020-07-23 14:56 ` Arnaldo Carvalho de Melo
2020-07-24 8:25 ` Athira Rajeev
2020-07-24 12:26 ` Ravi Bangoria
2020-07-24 18:13 ` Athira Rajeev
2020-07-17 14:38 ` [v3 13/15] tools/perf: Add perf tools support for extended register capability in powerpc Athira Rajeev
2020-07-21 6:03 ` kajoljain
2020-07-24 11:02 ` Ravi Bangoria
2020-07-24 18:02 ` Athira Rajeev
2020-07-17 14:38 ` [v3 14/15] powerpc/perf: Add extended regs support for power10 platform Athira Rajeev
2020-07-21 6:03 ` kajoljain
2020-07-17 14:38 ` [v3 15/15] tools/perf: Add perf tools support for extended regs in power10 Athira Rajeev
2020-07-21 6:04 ` kajoljain [this message]
2020-07-24 13:24 ` [v3 00/15] powerpc/perf: Add support for power10 PMU Hardware Michael Ellerman
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=0ea080de-8847-c4dd-dcb8-dd9d85529630@linux.ibm.com \
--to=kjain@linux.ibm.com \
--cc=acme@kernel.org \
--cc=atrajeev@linux.vnet.ibm.com \
--cc=ego@linux.vnet.ibm.com \
--cc=jolsa@kernel.org \
--cc=kvm-ppc@vger.kernel.org \
--cc=kvm@vger.kernel.org \
--cc=linuxppc-dev@lists.ozlabs.org \
--cc=maddy@linux.vnet.ibm.com \
--cc=mikey@neuling.org \
--cc=mpe@ellerman.id.au \
--cc=svaidyan@in.ibm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).