From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Woodhouse Subject: Re: [PATCH 2/2] x86/speculation: Support "Enhanced IBRS" on future CPUs Date: Fri, 16 Feb 2018 12:10:21 +0000 Message-ID: <1518783021.7876.34.camel@infradead.org> References: <1518449255-2182-1-git-send-email-dwmw@amazon.co.uk> <1518449255-2182-2-git-send-email-dwmw@amazon.co.uk> <7e2e5ad1-49b6-1fdb-4a62-8ad6aefc30a0@redhat.com> <1518509708.12890.33.camel@infradead.org> <27c85759-e662-d281-f8a0-0a80ca8ee18f@redhat.com> <1518517262.12890.43.camel@infradead.org> <1518518198.12890.48.camel@infradead.org> <02bd3fdd-1b73-6cab-fb09-38ba933396bd@redhat.com> <1518775136.7876.13.camel@infradead.org> <75287047-77a0-e0ff-c2e8-61c81641251e@redhat.com> <1518776517.7876.21.camel@infradead.org> Mime-Version: 1.0 Content-Type: multipart/signed; micalg="sha-256"; protocol="application/x-pkcs7-signature"; boundary="=-hNtnvu7IJ7EWRYYqbaRD" Cc: Ingo Molnar To: Paolo Bonzini , tglx@linutronix.de, x86@kernel.org, kvm@vger.kernel.org, torvalds@linux-foundation.org, linux-kernel@vger.kernel.org, arjan.van.de.ven@intel.com, dave.hansen@intel.com Return-path: In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org --=-hNtnvu7IJ7EWRYYqbaRD Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, 2018-02-16 at 12:04 +0100, Paolo Bonzini wrote: > On 16/02/2018 11:21, David Woodhouse wrote: > >=20 > > Why? With IBRS_ALL the guest *never* gets to affect the actual hardware > > MSR, which is always on. The MSR is purely an emulated no-op. Why does > > that affect migration? > Because even if the host has IBRS_ALL, as long as you want to migrate to > a system without IBRS_ALL the guest will likely not have it.=C2=A0=C2=A0Y= ou can > fake IBRS_ALL on the older system after migration, and forcing the guest > to always run with IBRS=3D1 even when in user mode; that is slow.=C2=A0= =C2=A0Or... No you can't; it's also a barrier. You can't just leave it on. > > Even if the guest doesn't have/support IBRS_ALL, and is frobbing the > > (now emulated) MSR on every kernel entry/exit, that's *still* going to > > be a metric shitload faster than what it *thought* it was doing. > > ... you are making every kernel entry/exit 3 times slower by adding two > KVM exits (both hypervisor traps and syscalls are in the 1000-1500 clock > cycles ballpark).=C2=A0=C2=A0That cannot be fast at all. I'm not convinced I care. It's still on a par with the performance of *actually* frobbing IBRS every time. If the guest cares about performance, they'll be using retpoline instead and not doing that. We really don't want to penalise the *host*, and other guests, for one guest which does stupid things. And if we have a conditional 'set IBRS back on because we're using IBRS_ALL and the guest had access to it' in the vmexit path, only the *first* clause (IBRS_ALL) of that condition can be done with alternatives. The other part is necessarily a runtime thing, and thus needs the 'else lfence' to make sure it really happens, penalising *all* guests. (Unless there's something else guaranteed to be serialising in that path but after Arjan mentioned it last time I took a quick look and didn't see anything unconditional). An alternative would be to put the SPEC_CTRL MSR into the list of MSRs=C2= =A0 to be automatically saved/reset at vmexit, but we've already carefully *changed* from doing that for the non-IBRS_ALL case because doing it manually in the host is faster. I don't know that we want that additional complexity =E2=80=94 that might be the last straw that makes us = tell Intel "no, in that case we don't want IBRS_ALL as it is. Define a new bit which is like IBRS_ALL but also promises that it's always like that and the IBRS bit in the MSR is a no-op". That new bit would be set on all future hardware except a small handful of current chips, I believe. I think we can live with trapping and emulating SPEC_CTRL for the guests which use it, for now. If we *really* want to explore optimising it somehow, there's nothing to prevent us doing that in a subsequent patch. --=-hNtnvu7IJ7EWRYYqbaRD Content-Type: application/x-pkcs7-signature; name="smime.p7s" Content-Disposition: attachment; filename="smime.p7s" Content-Transfer-Encoding: base64 MIAGCSqGSIb3DQEHAqCAMIACAQExDzANBglghkgBZQMEAgEFADCABgkqhkiG9w0BBwEAAKCCEFQw ggUxMIIEGaADAgECAhBNRhEyk/HZ7naOeTHWrzuAMA0GCSqGSIb3DQEBCwUAMIGXMQswCQYDVQQG EwJHQjEbMBkGA1UECBMSR3JlYXRlciBNYW5jaGVzdGVyMRAwDgYDVQQHEwdTYWxmb3JkMRowGAYD VQQKExFDT01PRE8gQ0EgTGltaXRlZDE9MDsGA1UEAxM0Q09NT0RPIFJTQSBDbGllbnQgQXV0aGVu dGljYXRpb24gYW5kIFNlY3VyZSBFbWFpbCBDQTAeFw0xNzEyMjEwMDAwMDBaFw0xODEyMjEyMzU5 NTlaMCQxIjAgBgkqhkiG9w0BCQEWE2R3bXcyQGluZnJhZGVhZC5vcmcwggEiMA0GCSqGSIb3DQEB AQUAA4IBDwAwggEKAoIBAQDgzLNWa18DNpGUj/ZeH0Sgz53ESIbzdPw3OJeuNP6jZhxZojbyfxbM hETscxI/Hj6UZ4a7sHm5BkVjlsB1Af2Za/PXUt8MmLAcPMHkMPGunvkUibEvblDvpqMkQZlaZM+t 5PqFmWkbehLaEvbpNY7dmEAAeKh4klTzJzrr5AAzaCQ32cA2e3+DEIv5O5l9ViMIjy/JM+xMQrfX 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