* [PATCH 1/2] target/i386: Add support for save PEBS registers
@ 2019-08-29 5:22 Luwei Kang
2019-08-29 5:22 ` [PATCH 2/2] target/i386: Add support for put/get " Luwei Kang
0 siblings, 1 reply; 3+ messages in thread
From: Luwei Kang @ 2019-08-29 5:22 UTC (permalink / raw)
To: pbonzini, rth, ehabkost; +Cc: qemu-devel, kvm, Luwei Kang
Intel processor introduce some hardware extensions that output PEBS record
to Intel PT buffer instead of DS area, so PEBS can be enabled in KVM guest
by PEBS output Intel PT. This patch adds a section for PEBS which use for
saves PEBS registers when the value is no-zero.
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
target/i386/cpu.h | 8 ++++++++
target/i386/machine.c | 41 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 49 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 5f6e3a0..d7cec36 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -409,6 +409,10 @@ typedef enum X86Seg {
#define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
+#define MSR_IA32_PEBS_ENABLE 0x3f1
+#define MSR_RELOAD_FIXED_CTR0 0x1309
+#define MSR_RELOAD_PMC0 0x14c1
+
#define MSR_MC0_CTL 0x400
#define MSR_MC0_STATUS 0x401
#define MSR_MC0_ADDR 0x402
@@ -1291,6 +1295,10 @@ typedef struct CPUX86State {
uint64_t msr_rtit_cr3_match;
uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
+ uint64_t msr_pebs_enable;
+ uint64_t msr_reload_fixed_ctr[MAX_FIXED_COUNTERS];
+ uint64_t msr_reload_pmc[MAX_GP_COUNTERS];
+
/* exception/interrupt handling */
int error_code;
int exception_is_int;
diff --git a/target/i386/machine.c b/target/i386/machine.c
index 2767b30..334d703 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -1274,6 +1274,46 @@ static const VMStateDescription vmstate_efer32 = {
};
#endif
+static bool pebs_enable_needed(void *opaque)
+{
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
+ int i;
+
+ if (env->msr_pebs_enable) {
+ return true;
+ }
+
+ for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
+ if (env->msr_reload_fixed_ctr[i]) {
+ return true;
+ }
+ }
+
+ for (i = 0; i < MAX_GP_COUNTERS; i++) {
+ if (env->msr_reload_pmc[i]) {
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static const VMStateDescription vmstate_msr_pebs = {
+ .name = "cpu/pebs",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = pebs_enable_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(env.msr_pebs_enable, X86CPU),
+ VMSTATE_UINT64_ARRAY(env.msr_reload_fixed_ctr, X86CPU,
+ MAX_FIXED_COUNTERS),
+ VMSTATE_UINT64_ARRAY(env.msr_reload_pmc, X86CPU,
+ MAX_GP_COUNTERS),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
VMStateDescription vmstate_x86_cpu = {
.name = "cpu",
.version_id = 12,
@@ -1407,6 +1447,7 @@ VMStateDescription vmstate_x86_cpu = {
#ifdef CONFIG_KVM
&vmstate_nested_state,
#endif
+ &vmstate_msr_pebs,
NULL
}
};
--
1.8.3.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2] target/i386: Add support for put/get PEBS registers
2019-08-29 5:22 [PATCH 1/2] target/i386: Add support for save PEBS registers Luwei Kang
@ 2019-08-29 5:22 ` Luwei Kang
2019-10-12 2:42 ` Eduardo Habkost
0 siblings, 1 reply; 3+ messages in thread
From: Luwei Kang @ 2019-08-29 5:22 UTC (permalink / raw)
To: pbonzini, rth, ehabkost; +Cc: qemu-devel, kvm, Luwei Kang
This patch add a new feature words for IA32_PERF_CAPABILITIES (RO)
register that serve to expose PEBS output Intel PT feature.
The registers relate with PEBS need to be set/get when PEBS output
Intel PT is supported in guest.
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
target/i386/cpu.c | 20 ++++++++++++++++++++
target/i386/cpu.h | 4 ++++
target/i386/kvm.c | 36 ++++++++++++++++++++++++++++++++++++
3 files changed, 60 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 9e0bac3..7fe34c0 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1244,6 +1244,26 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
},
},
+ [FEAT_PERF_CAPABILITIES] = {
+ .type = MSR_FEATURE_WORD,
+ .feat_names = {
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ "pebs-output-pt", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .msr = {
+ .index = MSR_IA32_PERF_CAPABILITIES,
+ .cpuid_dep = {
+ FEAT_1_ECX,
+ CPUID_EXT_PDCM,
+ },
+ },
+ },
};
typedef struct X86RegisterInfo32 {
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index d7cec36..0904004 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -347,6 +347,7 @@ typedef enum X86Seg {
#define MSR_IA32_PRED_CMD 0x49
#define MSR_IA32_CORE_CAPABILITY 0xcf
#define MSR_IA32_ARCH_CAPABILITIES 0x10a
+#define MSR_IA32_PERF_CAPABILITIES 0x345
#define MSR_IA32_TSCDEADLINE 0x6e0
#define FEATURE_CONTROL_LOCKED (1<<0)
@@ -503,6 +504,7 @@ typedef enum FeatureWord {
FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
FEAT_ARCH_CAPABILITIES,
FEAT_CORE_CAPABILITY,
+ FEAT_PERF_CAPABILITIES,
FEATURE_WORDS,
} FeatureWord;
@@ -754,6 +756,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
+#define MSR_PERF_CAP_PEBS_VIA_PT (1ULL << 16)
+
/* Supported Hyper-V Enlightenments */
#define HYPERV_FEAT_RELAXED 0
#define HYPERV_FEAT_VAPIC 1
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 8023c67..c0dcc13 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -2651,6 +2651,20 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
env->msr_rtit_addrs[i]);
}
+
+ if (env->features[FEAT_PERF_CAPABILITIES] &
+ MSR_PERF_CAP_PEBS_VIA_PT) {
+ kvm_msr_entry_add(cpu, MSR_IA32_PEBS_ENABLE,
+ env->msr_pebs_enable);
+ for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
+ kvm_msr_entry_add(cpu, MSR_RELOAD_FIXED_CTR0 + i,
+ env->msr_reload_fixed_ctr[i]);
+ }
+ for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
+ kvm_msr_entry_add(cpu, MSR_RELOAD_PMC0 + i,
+ env->msr_reload_pmc[i]);
+ }
+ }
}
/* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
@@ -2989,6 +3003,16 @@ static int kvm_get_msrs(X86CPU *cpu)
for (i = 0; i < addr_num; i++) {
kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
}
+
+ if (env->features[FEAT_PERF_CAPABILITIES] & MSR_PERF_CAP_PEBS_VIA_PT) {
+ kvm_msr_entry_add(cpu, MSR_IA32_PEBS_ENABLE, 0);
+ for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
+ kvm_msr_entry_add(cpu, MSR_RELOAD_FIXED_CTR0 + i, 0);
+ }
+ for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
+ kvm_msr_entry_add(cpu, MSR_RELOAD_PMC0 + i, 0);
+ }
+ }
}
ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
@@ -3268,6 +3292,18 @@ static int kvm_get_msrs(X86CPU *cpu)
case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
break;
+ case MSR_IA32_PEBS_ENABLE:
+ env->msr_pebs_enable = msrs[i].data;
+ break;
+ case MSR_RELOAD_FIXED_CTR0 ...
+ MSR_RELOAD_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
+ env->msr_reload_fixed_ctr[index - MSR_RELOAD_FIXED_CTR0] =
+ msrs[i].data;
+ break;
+ case MSR_RELOAD_PMC0 ...
+ MSR_RELOAD_PMC0 + MAX_GP_COUNTERS - 1:
+ env->msr_reload_fixed_ctr[index - MSR_RELOAD_PMC0] = msrs[i].data;
+ break;
}
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 2/2] target/i386: Add support for put/get PEBS registers
2019-08-29 5:22 ` [PATCH 2/2] target/i386: Add support for put/get " Luwei Kang
@ 2019-10-12 2:42 ` Eduardo Habkost
0 siblings, 0 replies; 3+ messages in thread
From: Eduardo Habkost @ 2019-10-12 2:42 UTC (permalink / raw)
To: Luwei Kang; +Cc: pbonzini, rth, qemu-devel, kvm
On Thu, Aug 29, 2019 at 01:22:55PM +0800, Luwei Kang wrote:
> This patch add a new feature words for IA32_PERF_CAPABILITIES (RO)
> register that serve to expose PEBS output Intel PT feature.
> The registers relate with PEBS need to be set/get when PEBS output
> Intel PT is supported in guest.
>
> Signed-off-by: Luwei Kang <luwei.kang@intel.com>
Sorry for taking so long to take a look at the series.
What's the status of the kernel KVM patches for this?
> ---
> target/i386/cpu.c | 20 ++++++++++++++++++++
> target/i386/cpu.h | 4 ++++
> target/i386/kvm.c | 36 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 60 insertions(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 9e0bac3..7fe34c0 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -1244,6 +1244,26 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
> },
> },
> },
> + [FEAT_PERF_CAPABILITIES] = {
> + .type = MSR_FEATURE_WORD,
> + .feat_names = {
> + NULL, NULL, NULL, NULL,
> + NULL, NULL, NULL, NULL,
> + NULL, NULL, NULL, NULL,
> + NULL, NULL, NULL, NULL,
> + "pebs-output-pt", NULL, NULL, NULL,
> + NULL, NULL, NULL, NULL,
> + NULL, NULL, NULL, NULL,
> + NULL, NULL, NULL, NULL,
> + },
> + .msr = {
> + .index = MSR_IA32_PERF_CAPABILITIES,
> + .cpuid_dep = {
> + FEAT_1_ECX,
> + CPUID_EXT_PDCM,
> + },
> + },
> + },
> };
>
> typedef struct X86RegisterInfo32 {
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index d7cec36..0904004 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -347,6 +347,7 @@ typedef enum X86Seg {
> #define MSR_IA32_PRED_CMD 0x49
> #define MSR_IA32_CORE_CAPABILITY 0xcf
> #define MSR_IA32_ARCH_CAPABILITIES 0x10a
> +#define MSR_IA32_PERF_CAPABILITIES 0x345
> #define MSR_IA32_TSCDEADLINE 0x6e0
>
> #define FEATURE_CONTROL_LOCKED (1<<0)
> @@ -503,6 +504,7 @@ typedef enum FeatureWord {
> FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
> FEAT_ARCH_CAPABILITIES,
> FEAT_CORE_CAPABILITY,
> + FEAT_PERF_CAPABILITIES,
> FEATURE_WORDS,
> } FeatureWord;
>
> @@ -754,6 +756,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
>
> #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
>
> +#define MSR_PERF_CAP_PEBS_VIA_PT (1ULL << 16)
> +
> /* Supported Hyper-V Enlightenments */
> #define HYPERV_FEAT_RELAXED 0
> #define HYPERV_FEAT_VAPIC 1
> diff --git a/target/i386/kvm.c b/target/i386/kvm.c
> index 8023c67..c0dcc13 100644
> --- a/target/i386/kvm.c
> +++ b/target/i386/kvm.c
> @@ -2651,6 +2651,20 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
> kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
> env->msr_rtit_addrs[i]);
> }
> +
> + if (env->features[FEAT_PERF_CAPABILITIES] &
> + MSR_PERF_CAP_PEBS_VIA_PT) {
> + kvm_msr_entry_add(cpu, MSR_IA32_PEBS_ENABLE,
> + env->msr_pebs_enable);
> + for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
> + kvm_msr_entry_add(cpu, MSR_RELOAD_FIXED_CTR0 + i,
> + env->msr_reload_fixed_ctr[i]);
> + }
> + for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
> + kvm_msr_entry_add(cpu, MSR_RELOAD_PMC0 + i,
> + env->msr_reload_pmc[i]);
> + }
> + }
> }
>
> /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
> @@ -2989,6 +3003,16 @@ static int kvm_get_msrs(X86CPU *cpu)
> for (i = 0; i < addr_num; i++) {
> kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
> }
> +
> + if (env->features[FEAT_PERF_CAPABILITIES] & MSR_PERF_CAP_PEBS_VIA_PT) {
> + kvm_msr_entry_add(cpu, MSR_IA32_PEBS_ENABLE, 0);
> + for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
> + kvm_msr_entry_add(cpu, MSR_RELOAD_FIXED_CTR0 + i, 0);
> + }
> + for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
> + kvm_msr_entry_add(cpu, MSR_RELOAD_PMC0 + i, 0);
> + }
> + }
> }
>
> ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
> @@ -3268,6 +3292,18 @@ static int kvm_get_msrs(X86CPU *cpu)
> case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
> env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
> break;
> + case MSR_IA32_PEBS_ENABLE:
> + env->msr_pebs_enable = msrs[i].data;
> + break;
> + case MSR_RELOAD_FIXED_CTR0 ...
> + MSR_RELOAD_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
> + env->msr_reload_fixed_ctr[index - MSR_RELOAD_FIXED_CTR0] =
> + msrs[i].data;
> + break;
> + case MSR_RELOAD_PMC0 ...
> + MSR_RELOAD_PMC0 + MAX_GP_COUNTERS - 1:
> + env->msr_reload_fixed_ctr[index - MSR_RELOAD_PMC0] = msrs[i].data;
> + break;
> }
> }
>
> --
> 1.8.3.1
>
--
Eduardo
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2019-10-12 2:42 UTC | newest]
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2019-08-29 5:22 [PATCH 1/2] target/i386: Add support for save PEBS registers Luwei Kang
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2019-10-12 2:42 ` Eduardo Habkost
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