From: Luwei Kang <luwei.kang@intel.com>
To: pbonzini@redhat.com, rkrcmar@redhat.com
Cc: sean.j.christopherson@intel.com, vkuznets@redhat.com,
wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org,
tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
hpa@zytor.com, x86@kernel.org, ak@linux.intel.com,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
Luwei Kang <luwei.kang@intel.com>
Subject: [RFC v1 1/9] KVM: x86: Add base address parameter for get_fixed_pmc function
Date: Thu, 29 Aug 2019 13:34:01 +0800 [thread overview]
Message-ID: <1567056849-14608-2-git-send-email-luwei.kang@intel.com> (raw)
In-Reply-To: <1567056849-14608-1-git-send-email-luwei.kang@intel.com>
PEBS output Inte PT introduces some new MSRs (MSR_RELOAD_FIXED_CTRx)
for fixed function counters that use for autoload the preset value
after writing out a PEBS event.
Introduce base MSRs address parameter to make this function can get
performance monitor counter structure by MSR_RELOAD_FIXED_CTRx registers.
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
arch/x86/kvm/pmu.h | 5 ++---
arch/x86/kvm/vmx/pmu_intel.c | 14 +++++++++-----
2 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h
index 58265f7..c62a1ff 100644
--- a/arch/x86/kvm/pmu.h
+++ b/arch/x86/kvm/pmu.h
@@ -93,10 +93,9 @@ static inline struct kvm_pmc *get_gp_pmc(struct kvm_pmu *pmu, u32 msr,
}
/* returns fixed PMC with the specified MSR */
-static inline struct kvm_pmc *get_fixed_pmc(struct kvm_pmu *pmu, u32 msr)
+static inline struct kvm_pmc *get_fixed_pmc(struct kvm_pmu *pmu, u32 msr,
+ int base)
{
- int base = MSR_CORE_PERF_FIXED_CTR0;
-
if (msr >= base && msr < base + pmu->nr_arch_fixed_counters)
return &pmu->fixed_counters[msr - base];
diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index 4dea0e0..01441be 100644
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
@@ -41,7 +41,8 @@ static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data)
u8 old_ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, i);
struct kvm_pmc *pmc;
- pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i);
+ pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i,
+ MSR_CORE_PERF_FIXED_CTR0);
if (old_ctrl == new_ctrl)
continue;
@@ -106,7 +107,8 @@ static struct kvm_pmc *intel_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx)
else {
u32 idx = pmc_idx - INTEL_PMC_IDX_FIXED;
- return get_fixed_pmc(pmu, idx + MSR_CORE_PERF_FIXED_CTR0);
+ return get_fixed_pmc(pmu, idx + MSR_CORE_PERF_FIXED_CTR0,
+ MSR_CORE_PERF_FIXED_CTR0);
}
}
@@ -155,7 +157,7 @@ static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
default:
ret = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0) ||
get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0) ||
- get_fixed_pmc(pmu, msr);
+ get_fixed_pmc(pmu, msr, MSR_CORE_PERF_FIXED_CTR0);
break;
}
@@ -185,7 +187,8 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
u64 val = pmc_read_counter(pmc);
*data = val & pmu->counter_bitmask[KVM_PMC_GP];
return 0;
- } else if ((pmc = get_fixed_pmc(pmu, msr))) {
+ } else if ((pmc = get_fixed_pmc(pmu, msr,
+ MSR_CORE_PERF_FIXED_CTR0))) {
u64 val = pmc_read_counter(pmc);
*data = val & pmu->counter_bitmask[KVM_PMC_FIXED];
return 0;
@@ -243,7 +246,8 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
else
pmc->counter = (s32)data;
return 0;
- } else if ((pmc = get_fixed_pmc(pmu, msr))) {
+ } else if ((pmc = get_fixed_pmc(pmu, msr,
+ MSR_CORE_PERF_FIXED_CTR0))) {
pmc->counter = data;
return 0;
} else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {
--
1.8.3.1
next prev parent reply other threads:[~2019-08-29 5:38 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-29 5:34 [RFC v1 0/9] PEBS enabling in KVM guest Luwei Kang
2019-08-29 5:34 ` Luwei Kang [this message]
2019-08-29 19:01 ` [RFC v1 1/9] KVM: x86: Add base address parameter for get_fixed_pmc function Jim Mattson
2019-08-30 0:01 ` Kang, Luwei
2019-08-29 21:10 ` Andi Kleen
2019-08-30 0:15 ` Kang, Luwei
2019-08-29 5:34 ` [RFC v1 2/9] KVM: x86: PEBS via Intel PT HW feature detection Luwei Kang
2019-08-29 5:34 ` [RFC v1 3/9] KVM: x86: Implement MSR_IA32_PEBS_ENABLE read/write emulation Luwei Kang
2019-08-29 21:20 ` Andi Kleen
2019-08-30 0:22 ` Kang, Luwei
2019-08-29 5:34 ` [RFC v1 4/9] KVM: x86: Implement counter reload MSRs " Luwei Kang
2019-08-29 5:34 ` [RFC v1 5/9] KVM: x86: Allocate performance counter for PEBS event Luwei Kang
2019-08-29 5:34 ` [RFC v1 6/9] KVM: x86: Add shadow value of PEBS status Luwei Kang
2019-08-29 5:34 ` [RFC v1 7/9] KVM: X86: Expose PDCM cpuid to guest Luwei Kang
2019-08-29 5:34 ` [RFC v1 8/9] KVM: X86: MSR_IA32_PERF_CAPABILITIES MSR emulation Luwei Kang
2019-08-29 5:34 ` [RFC v1 9/9] KVM: x86: Expose PEBS feature to guest Luwei Kang
2019-08-29 7:28 ` [RFC v1 0/9] PEBS enabling in KVM guest Peter Zijlstra
2019-08-29 8:11 ` Kang, Luwei
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