From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C82A4C433DF for ; Thu, 2 Jul 2020 16:31:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AE4C520760 for ; Thu, 2 Jul 2020 16:31:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726710AbgGBQb3 (ORCPT ); Thu, 2 Jul 2020 12:31:29 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:5434 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726465AbgGBQb3 (ORCPT ); Thu, 2 Jul 2020 12:31:29 -0400 Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 062G4EhL049989; Thu, 2 Jul 2020 12:31:28 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 320s2a71fc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 02 Jul 2020 12:31:28 -0400 Received: from m0098410.ppops.net (m0098410.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 062GKWce134787; Thu, 2 Jul 2020 12:31:27 -0400 Received: from ppma06ams.nl.ibm.com (66.31.33a9.ip4.static.sl-reverse.com [169.51.49.102]) by mx0a-001b2d01.pphosted.com with ESMTP id 320s2a71ea-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 02 Jul 2020 12:31:27 -0400 Received: from pps.filterd (ppma06ams.nl.ibm.com [127.0.0.1]) by ppma06ams.nl.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 062GMH0O019741; Thu, 2 Jul 2020 16:31:25 GMT Received: from b06cxnps3075.portsmouth.uk.ibm.com (d06relay10.portsmouth.uk.ibm.com [9.149.109.195]) by ppma06ams.nl.ibm.com with ESMTP id 31wwch5vyx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 02 Jul 2020 16:31:25 +0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 062GVN3235979308 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 2 Jul 2020 16:31:23 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0DDC811C06C; Thu, 2 Jul 2020 16:31:23 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8C32611C058; Thu, 2 Jul 2020 16:31:22 +0000 (GMT) Received: from oc3016276355.ibm.com (unknown [9.145.146.43]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 2 Jul 2020 16:31:22 +0000 (GMT) From: Pierre Morel To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, david@redhat.com, thuth@redhat.com, cohuck@redhat.com, drjones@redhat.com Subject: [kvm-unit-tests PATCH v10 1/9] s390x: saving regs for interrupts Date: Thu, 2 Jul 2020 18:31:12 +0200 Message-Id: <1593707480-23921-2-git-send-email-pmorel@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1593707480-23921-1-git-send-email-pmorel@linux.ibm.com> References: <1593707480-23921-1-git-send-email-pmorel@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-07-02_09:2020-07-02,2020-07-02 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 suspectscore=1 mlxlogscore=999 impostorscore=0 phishscore=0 cotscore=-2147483648 priorityscore=1501 adultscore=0 mlxscore=0 spamscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2007020111 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org If we use multiple source of interrupts, for example, using SCLP console to print information while using I/O interrupts, we need to have a re-entrant register saving interruption handling. Instead of saving at a static memory address, let's save the base registers, the floating point registers and the floating point control register on the stack in case of I/O interrupts Note that we keep the static register saving to recover from the RESET tests. Signed-off-by: Pierre Morel Acked-by: Janosch Frank Acked-by: Thomas Huth Acked-by: Cornelia Huck --- s390x/cstart64.S | 41 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/s390x/cstart64.S b/s390x/cstart64.S index e084f13..4e51150 100644 --- a/s390x/cstart64.S +++ b/s390x/cstart64.S @@ -118,6 +118,43 @@ memsetxc: lmg %r0, %r15, GEN_LC_SW_INT_GRS .endm +/* Save registers on the stack (r15), so we can have stacked interrupts. */ + .macro SAVE_REGS_STACK + /* Allocate a stack frame for 15 general registers */ + slgfi %r15, 15 * 8 + /* Store registers r0 to r14 on the stack */ + stmg %r0, %r14, 0(%r15) + /* Allocate a stack frame for 16 floating point registers */ + /* The size of a FP register is the size of an double word */ + slgfi %r15, 16 * 8 + /* Save fp register on stack: offset to SP is multiple of reg number */ + .irp i, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + std \i, \i * 8(%r15) + .endr + /* Save fpc, but keep stack aligned on 64bits */ + slgfi %r15, 8 + efpc %r0 + stg %r0, 0(%r15) + .endm + +/* Restore the register in reverse order */ + .macro RESTORE_REGS_STACK + /* Restore fpc */ + lfpc 0(%r15) + algfi %r15, 8 + /* Restore fp register from stack: SP still where it was left */ + /* and offset to SP is a multiple of reg number */ + .irp i, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + ld \i, \i * 8(%r15) + .endr + /* Now that we're done, rewind the stack pointer by 16 double word */ + algfi %r15, 16 * 8 + /* Load the registers from stack */ + lmg %r0, %r14, 0(%r15) + /* Rewind the stack by 15 double word */ + algfi %r15, 15 * 8 + .endm + .section .text /* * load_reset calling convention: @@ -185,9 +222,9 @@ mcck_int: lpswe GEN_LC_MCCK_OLD_PSW io_int: - SAVE_REGS + SAVE_REGS_STACK brasl %r14, handle_io_int - RESTORE_REGS + RESTORE_REGS_STACK lpswe GEN_LC_IO_OLD_PSW svc_int: -- 2.25.1