[PATCH v2 0/4] Expose new features for intel processor

[PATCH v2 0/4] Expose new features for intel processor

[Cathy Zhang]

This patchset is to expose two new features for intel
processors which support them, like Sapphire Rapids.
SERIALIZE is a faster serializing instruction which
does not modify registers, arithmetic flags or memory,
will not cause VM exit. TSX suspend load tracking
instruction aims to give a way to choose which memory
accesses do not need to be tracked in the TSX read set.

Changelog:
v2	Add kernel feature enumeration patch to fix build error

Cathy Zhang (2):
  x86: Expose SERIALIZE for supported cpuid
  x86: Expose TSX Suspend Load Address Tracking

Ricardo Neri (1):
  x86/cpufeatures: Add enumeration for SERIALIZE instruction

Kyung Min Park (1):
  x86/cpufeatures: Enumerate TSX suspend load address tracking
    instructions

 arch/x86/include/asm/cpufeatures.h | 2 ++
 arch/x86/kvm/cpuid.c               | 3 ++-
 2 files changed, 4 insertions(+), 1 deletion(-)

--
1.8.3.1

[PATCH v2 1/4] x86/cpufeatures: Add enumeration for SERIALIZE instruction

[Cathy Zhang]

This instruction gives software a way to force the processor to complete
all modifications to flags, registers and memory from previous instructions
and drain all buffered writes to memory before the next instruction is
fetched and executed.

The same effect can be obtained using the cpuid instruction. However,
cpuid causes modification on the eax, ebx, ecx, and ecx regiters; it
also causes a VM exit.

A processor supports SERIALIZE instruction if CPUID.0x0x.0x0:EDX[14] is
present. The CPU feature flag is shown as "serialize" in /proc/cpuinfo.

Detailed information on the instructions and CPUID feature flag SERIALIZE
can be found in the latest Intel Architecture Instruction Set Extensions
and Future Features Programming Reference and Intel 64 and IA-32
Architectures Software Developer's Manual.

Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 02dabc9..adf45cf 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -365,6 +365,7 @@
 #define X86_FEATURE_SRBDS_CTRL		(18*32+ 9) /* "" SRBDS mitigation MSR available */
 #define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */
 #define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */
+#define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
 #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
 #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */
 #define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */
-- 
1.8.3.1

[PATCH v2 2/4] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions

[Cathy Zhang]

Intel TSX suspend load tracking instructions aim to give a way to
choose which memory accesses do not need to be tracked in the TSX
read set. Add TSX suspend load tracking CPUID feature flag TSXLDTRK
for enumeration.

A processor supports Intel TSX suspend load address tracking if
CPUID.0x07.0x0:EDX[16] is present. Two instructions XSUSLDTRK, XRESLDTRK
are available when this feature is present.

The CPU feature flag is shown as "tsxldtrk" in /proc/cpuinfo.

Detailed information on the instructions and CPUID feature flag TSXLDTRK
can be found in the latest Intel Architecture Instruction Set Extensions
and Future Features Programming Reference and Intel 64 and IA-32
Architectures Software Developer's Manual.

Signed-off-by: Kyung Min Park <kyung.min.park@intel.com>
Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index adf45cf..34b66d7 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -366,6 +366,7 @@
 #define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */
 #define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */
 #define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
+#define X86_FEATURE_TSX_LDTRK           (18*32+16) /* TSX Suspend Load Address Tracking */
 #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
 #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */
 #define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */
-- 
1.8.3.1

[PATCH v2 3/4] x86: Expose SERIALIZE for supported cpuid

[Cathy Zhang]

SERIALIZE instruction is supported by intel processors,
like Sapphire Rapids. Expose it in KVM supported cpuid.

Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
---
 arch/x86/kvm/cpuid.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 8a294f9..e603aeb 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -341,7 +341,8 @@ void kvm_set_cpu_caps(void)
 	kvm_cpu_cap_mask(CPUID_7_EDX,
 		F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
 		F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
-		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM)
+		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
+		F(SERIALIZE)
 	);
 
 	/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
-- 
1.8.3.1

[PATCH v2 4/4] x86: Expose TSX Suspend Load Address Tracking

[Cathy Zhang]

TSX Suspend Load Address Tracking is supported by intel processors,
like Sapphire Rapids. Expose it in KVM supported cpuid.

Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
---
 arch/x86/kvm/cpuid.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index e603aeb..dcf48cc 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -342,7 +342,7 @@ void kvm_set_cpu_caps(void)
 		F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
 		F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
 		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
-		F(SERIALIZE)
+		F(SERIALIZE) | F(TSX_LDTRK)
 	);
 
 	/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
-- 
1.8.3.1

Re: [PATCH v2 2/4] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions

[Kyung Min Park]

Hi Cathy,

On Tue, 2020-07-07 at 10:16 +0800, Cathy Zhang wrote:
> Intel TSX suspend load tracking instructions aim to give a way to
> choose which memory accesses do not need to be tracked in the TSX
> read set. Add TSX suspend load tracking CPUID feature flag TSXLDTRK
> for enumeration.
> 
> A processor supports Intel TSX suspend load address tracking if
> CPUID.0x07.0x0:EDX[16] is present. Two instructions XSUSLDTRK,
> XRESLDTRK
> are available when this feature is present.
> 
> The CPU feature flag is shown as "tsxldtrk" in /proc/cpuinfo.
> 
> Detailed information on the instructions and CPUID feature flag
> TSXLDTRK
> can be found in the latest Intel Architecture Instruction Set
> Extensions
> and Future Features Programming Reference and Intel 64 and IA-32
> Architectures Software Developer's Manual.
> 
> Signed-off-by: Kyung Min Park <kyung.min.park@intel.com>
> Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
> ---
>  arch/x86/include/asm/cpufeatures.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h
> b/arch/x86/include/asm/cpufeatures.h
> index adf45cf..34b66d7 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -366,6 +366,7 @@
>  #define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU
> buffers */
>  #define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* ""
> TSX_FORCE_ABORT */
>  #define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE
> instruction */
> +#define X86_FEATURE_TSX_LDTRK           (18*32+16) /* TSX Suspend
> Load Address Tracking */

Since you are using the flag name to "TSX_LDTRK", the commit message
needs to be changed accordingly. The commit message is saying
"tsxldtrk", not "tsx_ldtrk".

>  #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
>  #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* ""
> Speculation Control (IBRS + IBPB) */
>  #define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single
> Thread Indirect Branch Predictors */

Re: [PATCH v2 2/4] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions

[Greg KH]

On Tue, Jul 07, 2020 at 10:16:21AM +0800, Cathy Zhang wrote:
> Intel TSX suspend load tracking instructions aim to give a way to
> choose which memory accesses do not need to be tracked in the TSX
> read set. Add TSX suspend load tracking CPUID feature flag TSXLDTRK
> for enumeration.
> 
> A processor supports Intel TSX suspend load address tracking if
> CPUID.0x07.0x0:EDX[16] is present. Two instructions XSUSLDTRK, XRESLDTRK
> are available when this feature is present.
> 
> The CPU feature flag is shown as "tsxldtrk" in /proc/cpuinfo.
> 
> Detailed information on the instructions and CPUID feature flag TSXLDTRK
> can be found in the latest Intel Architecture Instruction Set Extensions
> and Future Features Programming Reference and Intel 64 and IA-32
> Architectures Software Developer's Manual.
> 
> Signed-off-by: Kyung Min Park <kyung.min.park@intel.com>
> Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
> ---
>  arch/x86/include/asm/cpufeatures.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index adf45cf..34b66d7 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -366,6 +366,7 @@
>  #define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */
>  #define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */
>  #define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
> +#define X86_FEATURE_TSX_LDTRK           (18*32+16) /* TSX Suspend Load Address Tracking */

No tabs?

:(

Re: [PATCH v2 1/4] x86/cpufeatures: Add enumeration for SERIALIZE instruction

[Andy Lutomirski]

On Mon, Jul 6, 2020 at 7:21 PM Cathy Zhang <cathy.zhang@intel.com> wrote:
>
> This instruction gives software a way to force the processor to complete
> all modifications to flags, registers and memory from previous instructions
> and drain all buffered writes to memory before the next instruction is
> fetched and executed.
>
> The same effect can be obtained using the cpuid instruction. However,
> cpuid causes modification on the eax, ebx, ecx, and ecx regiters; it
> also causes a VM exit.
>
> A processor supports SERIALIZE instruction if CPUID.0x0x.0x0:EDX[14] is
> present. The CPU feature flag is shown as "serialize" in /proc/cpuinfo.
>
> Detailed information on the instructions and CPUID feature flag SERIALIZE
> can be found in the latest Intel Architecture Instruction Set Extensions
> and Future Features Programming Reference and Intel 64 and IA-32
> Architectures Software Developer's Manual.

Can you also wire this up so sync_core() uses it?

Thanks,
Andy

RE: [PATCH v2 0/4] Expose new features for intel processor

[Luck, Tony]

>Cathy Zhang (2):
>  x86: Expose SERIALIZE for supported cpuid
>  x86: Expose TSX Suspend Load Address Tracking

Having separate patches for adding the X86_FEATURE bits
is fine (provides space in the commit log to document what each
is for). In this case it also preserves the "Author" of each.

But you should combine patches 3 & 4 into a single patch. Making
two patches to each add one bit to the KVM cpuid code just looks
like you are trying to inflate your patch count.

-Tony

Re: [PATCH v2 1/4] x86/cpufeatures: Add enumeration for SERIALIZE instruction

[Ricardo Neri]

On Tue, Jul 07, 2020 at 09:36:15AM -0700, Andy Lutomirski wrote:
> On Mon, Jul 6, 2020 at 7:21 PM Cathy Zhang <cathy.zhang@intel.com> wrote:
> >
> > This instruction gives software a way to force the processor to complete
> > all modifications to flags, registers and memory from previous instructions
> > and drain all buffered writes to memory before the next instruction is
> > fetched and executed.
> >
> > The same effect can be obtained using the cpuid instruction. However,
> > cpuid causes modification on the eax, ebx, ecx, and ecx regiters; it
> > also causes a VM exit.
> >
> > A processor supports SERIALIZE instruction if CPUID.0x0x.0x0:EDX[14] is
> > present. The CPU feature flag is shown as "serialize" in /proc/cpuinfo.
> >
> > Detailed information on the instructions and CPUID feature flag SERIALIZE
> > can be found in the latest Intel Architecture Instruction Set Extensions
> > and Future Features Programming Reference and Intel 64 and IA-32
> > Architectures Software Developer's Manual.
> 
> Can you also wire this up so sync_core() uses it?

I am cc'ing Fenghua, who has volunteered to work on this. Addind support
for SERIALIZE in sync_core() should not block merging these patches,
correct?

Thanks and BR,
Ricardo

Re: [PATCH v2 2/4] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions

[Zhang, Cathy]

On 7/7/2020 5:40 PM, Greg KH wrote:
> On Tue, Jul 07, 2020 at 10:16:21AM +0800, Cathy Zhang wrote:
>> Intel TSX suspend load tracking instructions aim to give a way to
>> choose which memory accesses do not need to be tracked in the TSX
>> read set. Add TSX suspend load tracking CPUID feature flag TSXLDTRK
>> for enumeration.
>>
>> A processor supports Intel TSX suspend load address tracking if
>> CPUID.0x07.0x0:EDX[16] is present. Two instructions XSUSLDTRK, XRESLDTRK
>> are available when this feature is present.
>>
>> The CPU feature flag is shown as "tsxldtrk" in /proc/cpuinfo.
>>
>> Detailed information on the instructions and CPUID feature flag TSXLDTRK
>> can be found in the latest Intel Architecture Instruction Set Extensions
>> and Future Features Programming Reference and Intel 64 and IA-32
>> Architectures Software Developer's Manual.
>>
>> Signed-off-by: Kyung Min Park <kyung.min.park@intel.com>
>> Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
>> ---
>>   arch/x86/include/asm/cpufeatures.h | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
>> index adf45cf..34b66d7 100644
>> --- a/arch/x86/include/asm/cpufeatures.h
>> +++ b/arch/x86/include/asm/cpufeatures.h
>> @@ -366,6 +366,7 @@
>>   #define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */
>>   #define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */
>>   #define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
>> +#define X86_FEATURE_TSX_LDTRK           (18*32+16) /* TSX Suspend Load Address Tracking */
> No tabs?
>
> :(
Sorry, it's my fault. I wrongly pick up an older kernel patch version, 
the latest one has no such issue. It will be addressed in next version.

Re: [PATCH v2 3/4] x86: Expose SERIALIZE for supported cpuid

[Sean Christopherson]

On Tue, Jul 07, 2020 at 10:16:22AM +0800, Cathy Zhang wrote:
> SERIALIZE instruction is supported by intel processors,
> like Sapphire Rapids. Expose it in KVM supported cpuid.

Providing at least a rough overview of the instruction, e.g. its enumeration,
usage, fault rules, controls, etc... would be nice.  In isolation, the
changelog isn't remotely helpful in understanding the correctness of the
patch.

> Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
> ---
>  arch/x86/kvm/cpuid.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
> index 8a294f9..e603aeb 100644
> --- a/arch/x86/kvm/cpuid.c
> +++ b/arch/x86/kvm/cpuid.c
> @@ -341,7 +341,8 @@ void kvm_set_cpu_caps(void)
>  	kvm_cpu_cap_mask(CPUID_7_EDX,
>  		F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
>  		F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
> -		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM)
> +		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
> +		F(SERIALIZE)
>  	);
>  
>  	/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
> -- 
> 1.8.3.1
> 

Re: [PATCH v2 3/4] x86: Expose SERIALIZE for supported cpuid

[Zhang, Cathy]

On 7/14/2020 11:00 AM, Sean Christopherson wrote:
> On Tue, Jul 07, 2020 at 10:16:22AM +0800, Cathy Zhang wrote:
>> SERIALIZE instruction is supported by intel processors,
>> like Sapphire Rapids. Expose it in KVM supported cpuid.
> Providing at least a rough overview of the instruction, e.g. its enumeration,
> usage, fault rules, controls, etc... would be nice.  In isolation, the
> changelog isn't remotely helpful in understanding the correctness of the
> patch.
Thanks Sean! Add it in the next version.
>
>> Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
>> ---
>>   arch/x86/kvm/cpuid.c | 3 ++-
>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
>> index 8a294f9..e603aeb 100644
>> --- a/arch/x86/kvm/cpuid.c
>> +++ b/arch/x86/kvm/cpuid.c
>> @@ -341,7 +341,8 @@ void kvm_set_cpu_caps(void)
>>   	kvm_cpu_cap_mask(CPUID_7_EDX,
>>   		F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
>>   		F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
>> -		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM)
>> +		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
>> +		F(SERIALIZE)
>>   	);
>>   
>>   	/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
>> -- 
>> 1.8.3.1
>>

Re: [PATCH v2 3/4] x86: Expose SERIALIZE for supported cpuid

[hpa]

On July 14, 2020 3:42:08 PM PDT, "Zhang, Cathy" <cathy.zhang@intel.com> wrote:
>On 7/14/2020 11:00 AM, Sean Christopherson wrote:
>> On Tue, Jul 07, 2020 at 10:16:22AM +0800, Cathy Zhang wrote:
>>> SERIALIZE instruction is supported by intel processors,
>>> like Sapphire Rapids. Expose it in KVM supported cpuid.
>> Providing at least a rough overview of the instruction, e.g. its
>enumeration,
>> usage, fault rules, controls, etc... would be nice.  In isolation,
>the
>> changelog isn't remotely helpful in understanding the correctness of
>the
>> patch.
>Thanks Sean! Add it in the next version.
>>
>>> Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
>>> ---
>>>   arch/x86/kvm/cpuid.c | 3 ++-
>>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
>>> index 8a294f9..e603aeb 100644
>>> --- a/arch/x86/kvm/cpuid.c
>>> +++ b/arch/x86/kvm/cpuid.c
>>> @@ -341,7 +341,8 @@ void kvm_set_cpu_caps(void)
>>>   	kvm_cpu_cap_mask(CPUID_7_EDX,
>>>   		F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
>>>   		F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
>>> -		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM)
>>> +		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
>>> +		F(SERIALIZE)
>>>   	);
>>>   
>>>   	/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
>>> -- 
>>> 1.8.3.1
>>>

At least that one is easy: SERIALIZE is architecturally a NOP, but with hard serialization, like CPUID or IRET.

-- 
Sent from my Android device with K-9 Mail. Please excuse my brevity.

Re: [PATCH v2 3/4] x86: Expose SERIALIZE for supported cpuid

[Zhang, Cathy]

On 7/15/2020 7:05 AM, hpa@zytor.com wrote:
> On July 14, 2020 3:42:08 PM PDT, "Zhang, Cathy" <cathy.zhang@intel.com> wrote:
>> On 7/14/2020 11:00 AM, Sean Christopherson wrote:
>>> On Tue, Jul 07, 2020 at 10:16:22AM +0800, Cathy Zhang wrote:
>>>> SERIALIZE instruction is supported by intel processors,
>>>> like Sapphire Rapids. Expose it in KVM supported cpuid.
>>> Providing at least a rough overview of the instruction, e.g. its
>> enumeration,
>>> usage, fault rules, controls, etc... would be nice.  In isolation,
>> the
>>> changelog isn't remotely helpful in understanding the correctness of
>> the
>>> patch.
>> Thanks Sean! Add it in the next version.
>>>> Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
>>>> ---
>>>>    arch/x86/kvm/cpuid.c | 3 ++-
>>>>    1 file changed, 2 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
>>>> index 8a294f9..e603aeb 100644
>>>> --- a/arch/x86/kvm/cpuid.c
>>>> +++ b/arch/x86/kvm/cpuid.c
>>>> @@ -341,7 +341,8 @@ void kvm_set_cpu_caps(void)
>>>>    	kvm_cpu_cap_mask(CPUID_7_EDX,
>>>>    		F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
>>>>    		F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
>>>> -		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM)
>>>> +		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
>>>> +		F(SERIALIZE)
>>>>    	);
>>>>    
>>>>    	/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
>>>> -- 
>>>> 1.8.3.1
>>>>
> At least that one is easy: SERIALIZE is architecturally a NOP, but with hard serialization, like CPUID or IRET.
SERIALIZE does not modify registers, arithmetic flags or memory, which 
is different with CPUID.

Re: [PATCH v2 3/4] x86: Expose SERIALIZE for supported cpuid

[hpa]

On July 14, 2020 5:03:31 PM PDT, "Zhang, Cathy" <cathy.zhang@intel.com> wrote:
>On 7/15/2020 7:05 AM, hpa@zytor.com wrote:
>> On July 14, 2020 3:42:08 PM PDT, "Zhang, Cathy"
><cathy.zhang@intel.com> wrote:
>>> On 7/14/2020 11:00 AM, Sean Christopherson wrote:
>>>> On Tue, Jul 07, 2020 at 10:16:22AM +0800, Cathy Zhang wrote:
>>>>> SERIALIZE instruction is supported by intel processors,
>>>>> like Sapphire Rapids. Expose it in KVM supported cpuid.
>>>> Providing at least a rough overview of the instruction, e.g. its
>>> enumeration,
>>>> usage, fault rules, controls, etc... would be nice.  In isolation,
>>> the
>>>> changelog isn't remotely helpful in understanding the correctness
>of
>>> the
>>>> patch.
>>> Thanks Sean! Add it in the next version.
>>>>> Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
>>>>> ---
>>>>>    arch/x86/kvm/cpuid.c | 3 ++-
>>>>>    1 file changed, 2 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
>>>>> index 8a294f9..e603aeb 100644
>>>>> --- a/arch/x86/kvm/cpuid.c
>>>>> +++ b/arch/x86/kvm/cpuid.c
>>>>> @@ -341,7 +341,8 @@ void kvm_set_cpu_caps(void)
>>>>>    	kvm_cpu_cap_mask(CPUID_7_EDX,
>>>>>    		F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
>>>>>    		F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
>>>>> -		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM)
>>>>> +		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
>>>>> +		F(SERIALIZE)
>>>>>    	);
>>>>>    
>>>>>    	/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software.
>*/
>>>>> -- 
>>>>> 1.8.3.1
>>>>>
>> At least that one is easy: SERIALIZE is architecturally a NOP, but
>with hard serialization, like CPUID or IRET.
>SERIALIZE does not modify registers, arithmetic flags or memory, which 
>is different with CPUID.

That's what I meant with it being an architectural NOP.
-- 
Sent from my Android device with K-9 Mail. Please excuse my brevity.

Re: [PATCH v2 1/4] x86/cpufeatures: Add enumeration for SERIALIZE instruction

[Thomas Gleixner]

Ricardo Neri <ricardo.neri-calderon@linux.intel.com> writes:
> On Tue, Jul 07, 2020 at 09:36:15AM -0700, Andy Lutomirski wrote:
>> On Mon, Jul 6, 2020 at 7:21 PM Cathy Zhang <cathy.zhang@intel.com> wrote:
>> >
>> > This instruction gives software a way to force the processor to complete
>> > all modifications to flags, registers and memory from previous instructions
>> > and drain all buffered writes to memory before the next instruction is
>> > fetched and executed.
>> >
>> > The same effect can be obtained using the cpuid instruction. However,
>> > cpuid causes modification on the eax, ebx, ecx, and ecx regiters; it
>> > also causes a VM exit.
>> >
>> > A processor supports SERIALIZE instruction if CPUID.0x0x.0x0:EDX[14] is
>> > present. The CPU feature flag is shown as "serialize" in /proc/cpuinfo.
>> >
>> > Detailed information on the instructions and CPUID feature flag SERIALIZE
>> > can be found in the latest Intel Architecture Instruction Set Extensions
>> > and Future Features Programming Reference and Intel 64 and IA-32
>> > Architectures Software Developer's Manual.
>> 
>> Can you also wire this up so sync_core() uses it?
>
> I am cc'ing Fenghua, who has volunteered to work on this. Addind support
> for SERIALIZE in sync_core() should not block merging these patches,
> correct?

Come on. We are not serving KVM first before making this usable on bare
metal.

Thanks,

        tglx

Re: [PATCH v2 1/4] x86/cpufeatures: Add enumeration for SERIALIZE instruction

[Ricardo Neri]

On Thu, Jul 23, 2020 at 01:02:43AM +0200, Thomas Gleixner wrote:
> Ricardo Neri <ricardo.neri-calderon@linux.intel.com> writes:
> > On Tue, Jul 07, 2020 at 09:36:15AM -0700, Andy Lutomirski wrote:
> >> On Mon, Jul 6, 2020 at 7:21 PM Cathy Zhang <cathy.zhang@intel.com> wrote:
> >> >
> >> > This instruction gives software a way to force the processor to complete
> >> > all modifications to flags, registers and memory from previous instructions
> >> > and drain all buffered writes to memory before the next instruction is
> >> > fetched and executed.
> >> >
> >> > The same effect can be obtained using the cpuid instruction. However,
> >> > cpuid causes modification on the eax, ebx, ecx, and ecx regiters; it
> >> > also causes a VM exit.
> >> >
> >> > A processor supports SERIALIZE instruction if CPUID.0x0x.0x0:EDX[14] is
> >> > present. The CPU feature flag is shown as "serialize" in /proc/cpuinfo.
> >> >
> >> > Detailed information on the instructions and CPUID feature flag SERIALIZE
> >> > can be found in the latest Intel Architecture Instruction Set Extensions
> >> > and Future Features Programming Reference and Intel 64 and IA-32
> >> > Architectures Software Developer's Manual.
> >> 
> >> Can you also wire this up so sync_core() uses it?
> >
> > I am cc'ing Fenghua, who has volunteered to work on this. Addind support
> > for SERIALIZE in sync_core() should not block merging these patches,
> > correct?
> 
> Come on. We are not serving KVM first before making this usable on bare
> metal.

Hi Thomas,

I ended up implementing support for SERIALIZE in sync_core() I will be
posting patches for this in the next few days.

Thanks and BR,
Ricardo

Re: [PATCH v2 1/4] x86/cpufeatures: Add enumeration for SERIALIZE instruction

[Paolo Bonzini]

On 23/07/20 01:02, Thomas Gleixner wrote:
>> I am cc'ing Fenghua, who has volunteered to work on this. Addind support
>> for SERIALIZE in sync_core() should not block merging these patches,
>> correct?
> Come on. We are not serving KVM first before making this usable on bare
> metal.

This in the end was merged in 5.9, but: why not?  It is just an
instruction with no other support code needed in the kernel (or KVM for
that matter except for marking the CPUID bit as supported).  It is
common to run hosts with an older kernel than the guests, and by this
line of reasoning, we should not even have enabled support for FSGSBASE
in KVM.

Paolo