From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7595C433F7 for ; Tue, 28 Jul 2020 09:45:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A9EB020775 for ; Tue, 28 Jul 2020 09:45:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Bd+wINYD" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728561AbgG1JpV (ORCPT ); Tue, 28 Jul 2020 05:45:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48168 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728545AbgG1JpT (ORCPT ); Tue, 28 Jul 2020 05:45:19 -0400 Received: from mail-pg1-x541.google.com (mail-pg1-x541.google.com [IPv6:2607:f8b0:4864:20::541]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03D6DC061794; Tue, 28 Jul 2020 02:45:19 -0700 (PDT) Received: by mail-pg1-x541.google.com with SMTP id j19so11546407pgm.11; Tue, 28 Jul 2020 02:45:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ll8WCmZeOpOBPrLRP/0beycTFEf8dKZrUNMUWQ1/JDQ=; b=Bd+wINYDCUP8z22guocQAcON4oKrYDx2CgIgsz8nnitTQlq2y+JXpZ6GN/+kc010po POfHgEHzAud6glM01h6FgHQ98/JBoLPT2C+XcK64WAs0bZD9vSN4AoGJLvo/EBpvV/Ud 4AJjxLQPJyLxy9N0ZZ0Kve1ciIIsmicpsinl04IVkDxW0KLwFH6FIWf/RydET4VW+kkJ BueZlIgfCf1i6gAdX8sGoXbW8d6yXcqaCtr2CHmmkvbgS08rCMuARrAufwEmAw11eWA3 WpVTGBRbACsS1CrK+7xHJ19nt1guaMn1CS8qkrAuQh0ysVfSfUogVp2drqcDnxttXl4l paig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ll8WCmZeOpOBPrLRP/0beycTFEf8dKZrUNMUWQ1/JDQ=; b=hq8BOZRyaGh0dq6JxHPwKlHtKusesrjSouwaIn72jDhhLk1h8HDsDZ85Lb6mdE+Ps/ qYxFS+C7HRzcewzRIVZJ2ANEm50o2bBPS51V/erajWiZu1rACOcX19xoHA4JU25E3Jlq +JjfiuJOGoNIR1b1jT82ZQJUbB1YkhoDLQTd3R+HtNESz7zW6jS3jZer9BNxJzoNXUT1 efoUXu3/xBa13xGqw8EHYXcDZIrM+1+30Uwi5uk47ZKqFtsrNoP35BCMT+YXzxnHhjp/ nDRf6FT1czGSZGjWBJblgBhabA3gANh8ELowjSpiJmhJLFbfZCAVaXfApybvOXYzxLpN pNKQ== X-Gm-Message-State: AOAM533hZfKHa0zlBsKvUaFOKEwOROe9osKJzwGfZAcEM63QYPWygHaC wlyBn8OqFz4jpH1OpnXv04oFCUVE X-Google-Smtp-Source: ABdhPJzX4644pR5SThaJH2dX56DH72ENkeS4mx1iIiB2Au6Z2mLpx1MuGv3yo3As09M/O5xzIOYpOQ== X-Received: by 2002:a62:88d4:: with SMTP id l203mr23287682pfd.205.1595929518202; Tue, 28 Jul 2020 02:45:18 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.6]) by smtp.googlemail.com with ESMTPSA id r17sm17969173pfg.62.2020.07.28.02.45.15 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 Jul 2020 02:45:17 -0700 (PDT) From: Wanpeng Li X-Google-Original-From: Wanpeng Li To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel Subject: [PATCH v2 2/3] KVM: LAPIC: Set the APIC_TDCR settable bits Date: Tue, 28 Jul 2020 17:45:05 +0800 Message-Id: <1595929506-9203-2-git-send-email-wanpengli@tencent.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595929506-9203-1-git-send-email-wanpengli@tencent.com> References: <1595929506-9203-1-git-send-email-wanpengli@tencent.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Wanpeng Li It is a little different between Intel and AMD, Intel's bit 2 is 0 and AMD is reserved. On bare-metal, Intel will refuse to set APIC_TDCR once bits except 0, 1, 3 are setting, however, AMD will accept bits 0, 1, 3 and ignore other bits setting as patch does. Before the patch, we can get back anything what we set to the APIC_TDCR, this patch improves it. Signed-off-by: Wanpeng Li --- arch/x86/kvm/lapic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 4ce2ddd..8f7a14d 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2068,7 +2068,7 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) case APIC_TDCR: { uint32_t old_divisor = apic->divide_count; - kvm_lapic_set_reg(apic, APIC_TDCR, val); + kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb); update_divide_count(apic); if (apic->divide_count != old_divisor && apic->lapic_timer.period) { -- 2.7.4