From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF484C4338F for ; Fri, 6 Aug 2021 07:30:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D4BBF61179 for ; Fri, 6 Aug 2021 07:30:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243757AbhHFHa1 (ORCPT ); Fri, 6 Aug 2021 03:30:27 -0400 Received: from mga05.intel.com ([192.55.52.43]:16368 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241718AbhHFH36 (ORCPT ); Fri, 6 Aug 2021 03:29:58 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10067"; a="299913811" X-IronPort-AV: E=Sophos;i="5.84,299,1620716400"; d="scan'208";a="299913811" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2021 00:29:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,299,1620716400"; d="scan'208";a="513102468" Received: from michael-optiplex-9020.sh.intel.com ([10.239.159.182]) by FMSMGA003.fm.intel.com with ESMTP; 06 Aug 2021 00:29:39 -0700 From: Yang Weijiang To: pbonzini@redhat.com, jmattson@google.com, seanjc@google.com, vkuznets@redhat.com, wei.w.wang@intel.com, like.xu.linux@gmail.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Like Xu , Yang Weijiang Subject: [PATCH v7 10/15] KVM: x86: Add XSAVE Support for Architectural LBR Date: Fri, 6 Aug 2021 15:42:20 +0800 Message-Id: <1628235745-26566-11-git-send-email-weijiang.yang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1628235745-26566-1-git-send-email-weijiang.yang@intel.com> References: <1628235745-26566-1-git-send-email-weijiang.yang@intel.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu On processors supporting XSAVES and XRSTORS, Architectural LBR XSAVE support is enumerated from CPUID.(EAX=0DH, ECX=1):ECX[bit 15]. The detailed sub-leaf for Arch LBR is enumerated in CPUID.(0DH, 0FH). XSAVES provides a faster means than RDMSR for guest to read all LBRs. When guest IA32_XSS[bit 15] is set, the Arch LBR state can be saved using XSAVES and restored by XRSTORS with the appropriate RFBM. Signed-off-by: Like Xu Signed-off-by: Yang Weijiang --- arch/x86/kvm/vmx/vmx.c | 4 ++++ arch/x86/kvm/x86.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index f4d228a905c8..5f0545106d54 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7232,6 +7232,10 @@ static __init void vmx_set_cpu_caps(void) kvm_cpu_cap_clear(X86_FEATURE_INVPCID); if (vmx_pt_mode_is_host_guest()) kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT); + if (!cpu_has_vmx_arch_lbr()) { + kvm_cpu_cap_clear(X86_FEATURE_ARCH_LBR); + supported_xss &= ~XFEATURE_MASK_LBR; + } if (!enable_sgx) { kvm_cpu_cap_clear(X86_FEATURE_SGX); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index ef80370d825b..62db124c62a5 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -210,7 +210,7 @@ static struct kvm_user_return_msrs __percpu *user_return_msrs; | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ | XFEATURE_MASK_PKRU) -#define KVM_SUPPORTED_XSS 0 +#define KVM_SUPPORTED_XSS XFEATURE_MASK_LBR u64 __read_mostly host_efer; EXPORT_SYMBOL_GPL(host_efer); -- 2.25.1