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* [PATCH v8 0/3] KVM: x86: Enable user wait instructions
@ 2019-07-16  6:55 Tao Xu
  2019-07-16  6:55 ` [PATCH v8 1/3] KVM: x86: Add support for " Tao Xu
                   ` (3 more replies)
  0 siblings, 4 replies; 9+ messages in thread
From: Tao Xu @ 2019-07-16  6:55 UTC (permalink / raw)
  To: pbonzini, rkrcmar, sean.j.christopherson, corbet, tglx, mingo, bp, hpa
  Cc: kvm, linux-kernel, fenghua.yu, xiaoyao.li, jingqi.liu, tao3.xu

UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions.

UMONITOR arms address monitoring hardware using an address. A store
to an address within the specified address range triggers the
monitoring hardware to wake up the processor waiting in umwait.

UMWAIT instructs the processor to enter an implementation-dependent
optimized state while monitoring a range of addresses. The optimized
state may be either a light-weight power/performance optimized state
(c0.1 state) or an improved power/performance optimized state
(c0.2 state).

TPAUSE instructs the processor to enter an implementation-dependent
optimized state c0.1 or c0.2 state and wake up when time-stamp counter
reaches specified timeout.

Availability of the user wait instructions is indicated by the presence
of the CPUID feature flag WAITPKG CPUID.0x07.0x0:ECX[5].

The patches enable the umonitor, umwait and tpause features in KVM.
Because umwait and tpause can put a (psysical) CPU into a power saving
state, by default we dont't expose it to kvm and enable it only when
guest CPUID has it. If the instruction causes a delay, the amount
of time delayed is called here the physical delay. The physical delay is
first computed by determining the virtual delay (the time to delay
relative to the VM’s timestamp counter). 

The release document ref below link:
Intel 64 and IA-32 Architectures Software Developer's Manual,
https://software.intel.com/sites/default/files/\
managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf

Changelog:
v8:
	Add vmx_waitpkg_supported() helper (Sean)
	Add an accessor to expose umwait_control_cached (Sean)
	Set msr_ia32_umwait_control in vcpu_vmx u32 and raise #GP when
	[63:32] is set when rdmsr. (Sean)
	Introduce a common exit helper handle_unexpected_vmexit (Sean)
v7:
	Add nested support for user wait instructions (Paolo)
	Use the test on vmx->secondary_exec_control to replace
	guest_cpuid_has (Paolo)
v6:
	add check msr_info->host_initiated in get/set msr(Xiaoyao)
	restore the atomic_switch_umwait_control_msr()(Xiaoyao)

Tao Xu (3):
  KVM: x86: Add support for user wait instructions
  KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL
  KVM: vmx: Introduce handle_unexpected_vmexit and handle WAITPKG vmexit

 arch/x86/include/asm/vmx.h      |  1 +
 arch/x86/include/uapi/asm/vmx.h |  6 ++-
 arch/x86/kernel/cpu/umwait.c    |  6 +++
 arch/x86/kvm/cpuid.c            |  2 +-
 arch/x86/kvm/vmx/capabilities.h |  6 +++
 arch/x86/kvm/vmx/nested.c       |  5 ++
 arch/x86/kvm/vmx/vmx.c          | 83 ++++++++++++++++++++++++++-------
 arch/x86/kvm/vmx/vmx.h          |  9 ++++
 arch/x86/kvm/x86.c              |  1 +
 9 files changed, 101 insertions(+), 18 deletions(-)

-- 
2.20.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v8 1/3] KVM: x86: Add support for user wait instructions
  2019-07-16  6:55 [PATCH v8 0/3] KVM: x86: Enable user wait instructions Tao Xu
@ 2019-07-16  6:55 ` " Tao Xu
  2019-07-16  6:55 ` [PATCH v8 2/3] KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL Tao Xu
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 9+ messages in thread
From: Tao Xu @ 2019-07-16  6:55 UTC (permalink / raw)
  To: pbonzini, rkrcmar, sean.j.christopherson, corbet, tglx, mingo, bp, hpa
  Cc: kvm, linux-kernel, fenghua.yu, xiaoyao.li, jingqi.liu, tao3.xu

UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions.
This patch adds support for user wait instructions in KVM. Availability
of the user wait instructions is indicated by the presence of the CPUID
feature flag WAITPKG CPUID.0x07.0x0:ECX[5]. User wait instructions may
be executed at any privilege level, and use 32bit IA32_UMWAIT_CONTROL MSR
to set the maximum time.

The behavior of user wait instructions in VMX non-root operation is
determined first by the setting of the "enable user wait and pause"
secondary processor-based VM-execution control bit 26.
	If the VM-execution control is 0, UMONITOR/UMWAIT/TPAUSE cause
an invalid-opcode exception (#UD).
	If the VM-execution control is 1, treatment is based on the
setting of the “RDTSC exiting” VM-execution control. Because KVM never
enables RDTSC exiting, if the instruction causes a delay, the amount of
time delayed is called here the physical delay. The physical delay is
first computed by determining the virtual delay. If
IA32_UMWAIT_CONTROL[31:2] is zero, the virtual delay is the value in
EDX:EAX minus the value that RDTSC would return; if
IA32_UMWAIT_CONTROL[31:2] is not zero, the virtual delay is the minimum
of that difference and AND(IA32_UMWAIT_CONTROL,FFFFFFFCH).

Because umwait and tpause can put a (psysical) CPU into a power saving
state, by default we dont't expose it to kvm and enable it only when
guest CPUID has it.

Detailed information about user wait instructions can be found in the
latest Intel 64 and IA-32 Architectures Software Developer's Manual.

Co-developed-by: Jingqi Liu <jingqi.liu@intel.com>
Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---

Changes in v8:
    - Remove unnecessary comments (Sean)
    - Add vmx_waitpkg_supported() helper (Sean)
---
 arch/x86/include/asm/vmx.h      |  1 +
 arch/x86/kvm/cpuid.c            |  2 +-
 arch/x86/kvm/vmx/capabilities.h |  6 ++++++
 arch/x86/kvm/vmx/nested.c       |  1 +
 arch/x86/kvm/vmx/vmx.c          | 18 ++++++++++++++++++
 5 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index a39136b0d509..8f00882664d3 100644
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -69,6 +69,7 @@
 #define SECONDARY_EXEC_PT_USE_GPA		0x01000000
 #define SECONDARY_EXEC_MODE_BASED_EPT_EXEC	0x00400000
 #define SECONDARY_EXEC_TSC_SCALING              0x02000000
+#define SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE	0x04000000
 
 #define PIN_BASED_EXT_INTR_MASK                 0x00000001
 #define PIN_BASED_NMI_EXITING                   0x00000008
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 4992e7c99588..7d2cd4066f64 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -402,7 +402,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
 		F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ |
 		F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) |
 		F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) |
-		F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B);
+		F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/;
 
 	/* cpuid 7.0.edx*/
 	const u32 kvm_cpuid_7_0_edx_x86_features =
diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilities.h
index d6664ee3d127..7aa69716d516 100644
--- a/arch/x86/kvm/vmx/capabilities.h
+++ b/arch/x86/kvm/vmx/capabilities.h
@@ -247,6 +247,12 @@ static inline bool vmx_xsaves_supported(void)
 		SECONDARY_EXEC_XSAVES;
 }
 
+static inline bool vmx_waitpkg_supported(void)
+{
+	return vmcs_config.cpu_based_2nd_exec_ctrl &
+		SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
+}
+
 static inline bool cpu_has_vmx_tsc_scaling(void)
 {
 	return vmcs_config.cpu_based_2nd_exec_ctrl &
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index 46af3a5e9209..a4d5da34b306 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -2048,6 +2048,7 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
 				  SECONDARY_EXEC_ENABLE_INVPCID |
 				  SECONDARY_EXEC_RDTSCP |
 				  SECONDARY_EXEC_XSAVES |
+				  SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
 				  SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
 				  SECONDARY_EXEC_APIC_REGISTER_VIRT |
 				  SECONDARY_EXEC_ENABLE_VMFUNC);
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index d98eac371c0a..d4ee22ff7ccc 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -2247,6 +2247,7 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
 			SECONDARY_EXEC_RDRAND_EXITING |
 			SECONDARY_EXEC_ENABLE_PML |
 			SECONDARY_EXEC_TSC_SCALING |
+			SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
 			SECONDARY_EXEC_PT_USE_GPA |
 			SECONDARY_EXEC_PT_CONCEAL_VMX |
 			SECONDARY_EXEC_ENABLE_VMFUNC |
@@ -3984,6 +3985,23 @@ static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
 		}
 	}
 
+	if (vmx_waitpkg_supported()) {
+		bool waitpkg_enabled =
+			guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
+
+		if (!waitpkg_enabled)
+			exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
+
+		if (nested) {
+			if (waitpkg_enabled)
+				vmx->nested.msrs.secondary_ctls_high |=
+					SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
+			else
+				vmx->nested.msrs.secondary_ctls_high &=
+					~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
+		}
+	}
+
 	vmx->secondary_exec_control = exec_control;
 }
 
-- 
2.20.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v8 2/3] KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL
  2019-07-16  6:55 [PATCH v8 0/3] KVM: x86: Enable user wait instructions Tao Xu
  2019-07-16  6:55 ` [PATCH v8 1/3] KVM: x86: Add support for " Tao Xu
@ 2019-07-16  6:55 ` Tao Xu
  2019-07-16  6:55 ` [PATCH v8 3/3] KVM: vmx: Introduce handle_unexpected_vmexit and handle WAITPKG vmexit Tao Xu
  2019-07-19  6:31 ` [PATCH v8 0/3] KVM: x86: Enable user wait instructions Tao Xu
  3 siblings, 0 replies; 9+ messages in thread
From: Tao Xu @ 2019-07-16  6:55 UTC (permalink / raw)
  To: pbonzini, rkrcmar, sean.j.christopherson, corbet, tglx, mingo, bp, hpa
  Cc: kvm, linux-kernel, fenghua.yu, xiaoyao.li, jingqi.liu, tao3.xu

UMWAIT and TPAUSE instructions use 32bit IA32_UMWAIT_CONTROL at MSR index
E1H to determines the maximum time in TSC-quanta that the processor can
reside in either C0.1 or C0.2.

This patch emulates MSR IA32_UMWAIT_CONTROL in guest and differentiate
IA32_UMWAIT_CONTROL between host and guest. The variable
mwait_control_cached in arch/x86/kernel/cpu/umwait.c caches the MSR value,
so this patch uses it to avoid frequently rdmsr of IA32_UMWAIT_CONTROL.

Co-developed-by: Jingqi Liu <jingqi.liu@intel.com>
Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---

Changes in v8:
    - Add an accessor to expose umwait_control_cached (Sean)
    - Set msr_ia32_umwait_control in vcpu_vmx u32 and raise #GP when
      [63:32] is set when rdmsr. (Sean)
---
 arch/x86/kernel/cpu/umwait.c |  6 ++++++
 arch/x86/kvm/vmx/vmx.c       | 37 ++++++++++++++++++++++++++++++++++++
 arch/x86/kvm/vmx/vmx.h       |  9 +++++++++
 arch/x86/kvm/x86.c           |  1 +
 4 files changed, 53 insertions(+)

diff --git a/arch/x86/kernel/cpu/umwait.c b/arch/x86/kernel/cpu/umwait.c
index 6a204e7336c1..e7344be24a74 100644
--- a/arch/x86/kernel/cpu/umwait.c
+++ b/arch/x86/kernel/cpu/umwait.c
@@ -17,6 +17,12 @@
  */
 static u32 umwait_control_cached = UMWAIT_CTRL_VAL(100000, UMWAIT_C02_ENABLE);
 
+u32 get_umwait_control_msr(void)
+{
+	return umwait_control_cached;
+}
+EXPORT_SYMBOL_GPL(get_umwait_control_msr);
+
 /*
  * Serialize access to umwait_control_cached and IA32_UMWAIT_CONTROL MSR in
  * the sysfs write functions.
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index d4ee22ff7ccc..0224b087aad3 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -1676,6 +1676,12 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 #endif
 	case MSR_EFER:
 		return kvm_get_msr_common(vcpu, msr_info);
+	case MSR_IA32_UMWAIT_CONTROL:
+		if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
+			return 1;
+
+		msr_info->data = vmx->msr_ia32_umwait_control;
+		break;
 	case MSR_IA32_SPEC_CTRL:
 		if (!msr_info->host_initiated &&
 		    !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
@@ -1838,6 +1844,16 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 			return 1;
 		vmcs_write64(GUEST_BNDCFGS, data);
 		break;
+	case MSR_IA32_UMWAIT_CONTROL:
+		if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
+			return 1;
+
+		/* The reserved bit 1 and non-32 bit [63:32] should be zero */
+		if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
+			return 1;
+
+		vmx->msr_ia32_umwait_control = data;
+		break;
 	case MSR_IA32_SPEC_CTRL:
 		if (!msr_info->host_initiated &&
 		    !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
@@ -4137,6 +4153,8 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
 	vmx->rmode.vm86_active = 0;
 	vmx->spec_ctrl = 0;
 
+	vmx->msr_ia32_umwait_control = 0;
+
 	vcpu->arch.microcode_version = 0x100000000ULL;
 	vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
 	kvm_set_cr8(vcpu, 0);
@@ -6350,6 +6368,23 @@ static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
 					msrs[i].host, false);
 }
 
+static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
+{
+	u32 host_umwait_control;
+
+	if (!vmx_has_waitpkg(vmx))
+		return;
+
+	host_umwait_control = get_umwait_control_msr();
+
+	if (vmx->msr_ia32_umwait_control != host_umwait_control)
+		add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
+			vmx->msr_ia32_umwait_control,
+			host_umwait_control, false);
+	else
+		clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
+}
+
 static void vmx_arm_hv_timer(struct vcpu_vmx *vmx, u32 val)
 {
 	vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, val);
@@ -6458,6 +6493,8 @@ static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
 
 	atomic_switch_perf_msrs(vmx);
 
+	atomic_switch_umwait_control_msr(vmx);
+
 	vmx_update_hv_timer(vcpu);
 
 	/*
diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h
index 61128b48c503..8e4869322eff 100644
--- a/arch/x86/kvm/vmx/vmx.h
+++ b/arch/x86/kvm/vmx/vmx.h
@@ -14,6 +14,8 @@
 extern const u32 vmx_msr_index[];
 extern u64 host_efer;
 
+extern u32 get_umwait_control_msr(void);
+
 #define MSR_TYPE_R	1
 #define MSR_TYPE_W	2
 #define MSR_TYPE_RW	3
@@ -194,6 +196,7 @@ struct vcpu_vmx {
 #endif
 
 	u64		      spec_ctrl;
+	u32		      msr_ia32_umwait_control;
 
 	u32 vm_entry_controls_shadow;
 	u32 vm_exit_controls_shadow;
@@ -523,6 +526,12 @@ static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx)
 	vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
 }
 
+static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
+{
+	return vmx->secondary_exec_control &
+		SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
+}
+
 void dump_vmcs(void);
 
 #endif /* __KVM_X86_VMX_H */
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 63bb1ee8258e..e914e4d03cce 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1136,6 +1136,7 @@ static u32 msrs_to_save[] = {
 	MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
 	MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
 	MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
+	MSR_IA32_UMWAIT_CONTROL,
 };
 
 static unsigned num_msrs_to_save;
-- 
2.20.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v8 3/3] KVM: vmx: Introduce handle_unexpected_vmexit and handle WAITPKG vmexit
  2019-07-16  6:55 [PATCH v8 0/3] KVM: x86: Enable user wait instructions Tao Xu
  2019-07-16  6:55 ` [PATCH v8 1/3] KVM: x86: Add support for " Tao Xu
  2019-07-16  6:55 ` [PATCH v8 2/3] KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL Tao Xu
@ 2019-07-16  6:55 ` Tao Xu
  2019-07-19  6:31 ` [PATCH v8 0/3] KVM: x86: Enable user wait instructions Tao Xu
  3 siblings, 0 replies; 9+ messages in thread
From: Tao Xu @ 2019-07-16  6:55 UTC (permalink / raw)
  To: pbonzini, rkrcmar, sean.j.christopherson, corbet, tglx, mingo, bp, hpa
  Cc: kvm, linux-kernel, fenghua.yu, xiaoyao.li, jingqi.liu, tao3.xu

As the latest Intel 64 and IA-32 Architectures Software Developer's
Manual, UMWAIT and TPAUSE instructions cause a VM exit if the
RDTSC exiting and enable user wait and pause VM-execution
controls are both 1.

Because KVM never enable RDTSC exiting, the vm-exit for UMWAIT and TPAUSE
should never happen. Considering EXIT_REASON_XSAVES and
EXIT_REASON_XRSTORS is also unexpected VM-exit for KVM. Introduce a common
exit helper handle_unexpected_vmexit() to handle these unexpected VM-exit.

Suggested-by: Sean Christopherson <sean.j.christopherson@intel.com>
Co-developed-by: Jingqi Liu <jingqi.liu@intel.com>
Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---

Changes in v8:
    - Introduce a common exit helper handle_unexpected_vmexit (Sean)
---
 arch/x86/include/uapi/asm/vmx.h |  6 +++++-
 arch/x86/kvm/vmx/nested.c       |  4 ++++
 arch/x86/kvm/vmx/vmx.c          | 28 ++++++++++++----------------
 3 files changed, 21 insertions(+), 17 deletions(-)

diff --git a/arch/x86/include/uapi/asm/vmx.h b/arch/x86/include/uapi/asm/vmx.h
index d213ec5c3766..d88d7a68849b 100644
--- a/arch/x86/include/uapi/asm/vmx.h
+++ b/arch/x86/include/uapi/asm/vmx.h
@@ -85,6 +85,8 @@
 #define EXIT_REASON_PML_FULL            62
 #define EXIT_REASON_XSAVES              63
 #define EXIT_REASON_XRSTORS             64
+#define EXIT_REASON_UMWAIT              67
+#define EXIT_REASON_TPAUSE              68
 
 #define VMX_EXIT_REASONS \
 	{ EXIT_REASON_EXCEPTION_NMI,         "EXCEPTION_NMI" }, \
@@ -142,7 +144,9 @@
 	{ EXIT_REASON_RDSEED,                "RDSEED" }, \
 	{ EXIT_REASON_PML_FULL,              "PML_FULL" }, \
 	{ EXIT_REASON_XSAVES,                "XSAVES" }, \
-	{ EXIT_REASON_XRSTORS,               "XRSTORS" }
+	{ EXIT_REASON_XRSTORS,               "XRSTORS" }, \
+	{ EXIT_REASON_UMWAIT,                "UMWAIT" }, \
+	{ EXIT_REASON_TPAUSE,                "TPAUSE" }
 
 #define VMX_ABORT_SAVE_GUEST_MSR_FAIL        1
 #define VMX_ABORT_LOAD_HOST_PDPTE_FAIL       2
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index a4d5da34b306..12a162a2d798 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -5213,6 +5213,10 @@ bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
 	case EXIT_REASON_ENCLS:
 		/* SGX is never exposed to L1 */
 		return false;
+	case EXIT_REASON_UMWAIT:
+	case EXIT_REASON_TPAUSE:
+		return nested_cpu_has2(vmcs12,
+			SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE);
 	default:
 		return true;
 	}
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 0224b087aad3..db5bdc468f70 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -4967,20 +4967,6 @@ static int handle_xsetbv(struct kvm_vcpu *vcpu)
 	return 1;
 }
 
-static int handle_xsaves(struct kvm_vcpu *vcpu)
-{
-	kvm_skip_emulated_instruction(vcpu);
-	WARN(1, "this should never happen\n");
-	return 1;
-}
-
-static int handle_xrstors(struct kvm_vcpu *vcpu)
-{
-	kvm_skip_emulated_instruction(vcpu);
-	WARN(1, "this should never happen\n");
-	return 1;
-}
-
 static int handle_apic_access(struct kvm_vcpu *vcpu)
 {
 	if (likely(fasteoi)) {
@@ -5499,6 +5485,14 @@ static int handle_encls(struct kvm_vcpu *vcpu)
 	return 1;
 }
 
+static int handle_unexpected_vmexit(struct kvm_vcpu *vcpu)
+{
+	kvm_skip_emulated_instruction(vcpu);
+	WARN_ONCE(1, "Unexpected VM-Exit Reason = 0x%x",
+		vmcs_read32(VM_EXIT_REASON));
+	return 1;
+}
+
 /*
  * The exit handlers return 1 if the exit was handled fully and guest execution
  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
@@ -5550,13 +5544,15 @@ static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
 	[EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
 	[EXIT_REASON_RDRAND]                  = handle_invalid_op,
 	[EXIT_REASON_RDSEED]                  = handle_invalid_op,
-	[EXIT_REASON_XSAVES]                  = handle_xsaves,
-	[EXIT_REASON_XRSTORS]                 = handle_xrstors,
+	[EXIT_REASON_XSAVES]                  = handle_unexpected_vmexit,
+	[EXIT_REASON_XRSTORS]                 = handle_unexpected_vmexit,
 	[EXIT_REASON_PML_FULL]		      = handle_pml_full,
 	[EXIT_REASON_INVPCID]                 = handle_invpcid,
 	[EXIT_REASON_VMFUNC]		      = handle_vmx_instruction,
 	[EXIT_REASON_PREEMPTION_TIMER]	      = handle_preemption_timer,
 	[EXIT_REASON_ENCLS]		      = handle_encls,
+	[EXIT_REASON_UMWAIT]                  = handle_unexpected_vmexit,
+	[EXIT_REASON_TPAUSE]                  = handle_unexpected_vmexit,
 };
 
 static const int kvm_vmx_max_exit_handlers =
-- 
2.20.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v8 0/3] KVM: x86: Enable user wait instructions
  2019-07-16  6:55 [PATCH v8 0/3] KVM: x86: Enable user wait instructions Tao Xu
                   ` (2 preceding siblings ...)
  2019-07-16  6:55 ` [PATCH v8 3/3] KVM: vmx: Introduce handle_unexpected_vmexit and handle WAITPKG vmexit Tao Xu
@ 2019-07-19  6:31 ` Tao Xu
  2019-07-19 17:18   ` Paolo Bonzini
  3 siblings, 1 reply; 9+ messages in thread
From: Tao Xu @ 2019-07-19  6:31 UTC (permalink / raw)
  To: pbonzini, rkrcmar, sean.j.christopherson, corbet, tglx, mingo, bp, hpa
  Cc: kvm, linux-kernel, fenghua.yu, xiaoyao.li, jingqi.liu

Ping for comments :)

On 7/16/2019 2:55 PM, Tao Xu wrote:
> UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions.
> 
> UMONITOR arms address monitoring hardware using an address. A store
> to an address within the specified address range triggers the
> monitoring hardware to wake up the processor waiting in umwait.
> 
> UMWAIT instructs the processor to enter an implementation-dependent
> optimized state while monitoring a range of addresses. The optimized
> state may be either a light-weight power/performance optimized state
> (c0.1 state) or an improved power/performance optimized state
> (c0.2 state).
> 
> TPAUSE instructs the processor to enter an implementation-dependent
> optimized state c0.1 or c0.2 state and wake up when time-stamp counter
> reaches specified timeout.
> 
> Availability of the user wait instructions is indicated by the presence
> of the CPUID feature flag WAITPKG CPUID.0x07.0x0:ECX[5].
> 
> The patches enable the umonitor, umwait and tpause features in KVM.
> Because umwait and tpause can put a (psysical) CPU into a power saving
> state, by default we dont't expose it to kvm and enable it only when
> guest CPUID has it. If the instruction causes a delay, the amount
> of time delayed is called here the physical delay. The physical delay is
> first computed by determining the virtual delay (the time to delay
> relative to the VM’s timestamp counter).
> 
> The release document ref below link:
> Intel 64 and IA-32 Architectures Software Developer's Manual,
> https://software.intel.com/sites/default/files/\
> managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf
> 
> Changelog:
> v8:
> 	Add vmx_waitpkg_supported() helper (Sean)
> 	Add an accessor to expose umwait_control_cached (Sean)
> 	Set msr_ia32_umwait_control in vcpu_vmx u32 and raise #GP when
> 	[63:32] is set when rdmsr. (Sean)
> 	Introduce a common exit helper handle_unexpected_vmexit (Sean)
> v7:
> 	Add nested support for user wait instructions (Paolo)
> 	Use the test on vmx->secondary_exec_control to replace
> 	guest_cpuid_has (Paolo)
> v6:
> 	add check msr_info->host_initiated in get/set msr(Xiaoyao)
> 	restore the atomic_switch_umwait_control_msr()(Xiaoyao)
> 
> Tao Xu (3):
>    KVM: x86: Add support for user wait instructions
>    KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL
>    KVM: vmx: Introduce handle_unexpected_vmexit and handle WAITPKG vmexit
> 
>   arch/x86/include/asm/vmx.h      |  1 +
>   arch/x86/include/uapi/asm/vmx.h |  6 ++-
>   arch/x86/kernel/cpu/umwait.c    |  6 +++
>   arch/x86/kvm/cpuid.c            |  2 +-
>   arch/x86/kvm/vmx/capabilities.h |  6 +++
>   arch/x86/kvm/vmx/nested.c       |  5 ++
>   arch/x86/kvm/vmx/vmx.c          | 83 ++++++++++++++++++++++++++-------
>   arch/x86/kvm/vmx/vmx.h          |  9 ++++
>   arch/x86/kvm/x86.c              |  1 +
>   9 files changed, 101 insertions(+), 18 deletions(-)
> 


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v8 0/3] KVM: x86: Enable user wait instructions
  2019-07-19  6:31 ` [PATCH v8 0/3] KVM: x86: Enable user wait instructions Tao Xu
@ 2019-07-19 17:18   ` Paolo Bonzini
  2019-07-20  7:14     ` Tao Xu
  2019-09-16  1:28     ` Tao Xu
  0 siblings, 2 replies; 9+ messages in thread
From: Paolo Bonzini @ 2019-07-19 17:18 UTC (permalink / raw)
  To: Tao Xu, rkrcmar, sean.j.christopherson, corbet, tglx, mingo, bp, hpa
  Cc: kvm, linux-kernel, fenghua.yu, xiaoyao.li, jingqi.liu

On 19/07/19 08:31, Tao Xu wrote:
> Ping for comments :)

Hi, I'll look at it for 5.4, right after the merge window.

Paolo

> On 7/16/2019 2:55 PM, Tao Xu wrote:
>> UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions.
>>
>> UMONITOR arms address monitoring hardware using an address. A store
>> to an address within the specified address range triggers the
>> monitoring hardware to wake up the processor waiting in umwait.
>>
>> UMWAIT instructs the processor to enter an implementation-dependent
>> optimized state while monitoring a range of addresses. The optimized
>> state may be either a light-weight power/performance optimized state
>> (c0.1 state) or an improved power/performance optimized state
>> (c0.2 state).
>>
>> TPAUSE instructs the processor to enter an implementation-dependent
>> optimized state c0.1 or c0.2 state and wake up when time-stamp counter
>> reaches specified timeout.
>>
>> Availability of the user wait instructions is indicated by the presence
>> of the CPUID feature flag WAITPKG CPUID.0x07.0x0:ECX[5].
>>
>> The patches enable the umonitor, umwait and tpause features in KVM.
>> Because umwait and tpause can put a (psysical) CPU into a power saving
>> state, by default we dont't expose it to kvm and enable it only when
>> guest CPUID has it. If the instruction causes a delay, the amount
>> of time delayed is called here the physical delay. The physical delay is
>> first computed by determining the virtual delay (the time to delay
>> relative to the VM’s timestamp counter).
>>
>> The release document ref below link:
>> Intel 64 and IA-32 Architectures Software Developer's Manual,
>> https://software.intel.com/sites/default/files/\
>> managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf
>>
>> Changelog:
>> v8:
>>     Add vmx_waitpkg_supported() helper (Sean)
>>     Add an accessor to expose umwait_control_cached (Sean)
>>     Set msr_ia32_umwait_control in vcpu_vmx u32 and raise #GP when
>>     [63:32] is set when rdmsr. (Sean)
>>     Introduce a common exit helper handle_unexpected_vmexit (Sean)
>> v7:
>>     Add nested support for user wait instructions (Paolo)
>>     Use the test on vmx->secondary_exec_control to replace
>>     guest_cpuid_has (Paolo)
>> v6:
>>     add check msr_info->host_initiated in get/set msr(Xiaoyao)
>>     restore the atomic_switch_umwait_control_msr()(Xiaoyao)
>>
>> Tao Xu (3):
>>    KVM: x86: Add support for user wait instructions
>>    KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL
>>    KVM: vmx: Introduce handle_unexpected_vmexit and handle WAITPKG vmexit
>>
>>   arch/x86/include/asm/vmx.h      |  1 +
>>   arch/x86/include/uapi/asm/vmx.h |  6 ++-
>>   arch/x86/kernel/cpu/umwait.c    |  6 +++
>>   arch/x86/kvm/cpuid.c            |  2 +-
>>   arch/x86/kvm/vmx/capabilities.h |  6 +++
>>   arch/x86/kvm/vmx/nested.c       |  5 ++
>>   arch/x86/kvm/vmx/vmx.c          | 83 ++++++++++++++++++++++++++-------
>>   arch/x86/kvm/vmx/vmx.h          |  9 ++++
>>   arch/x86/kvm/x86.c              |  1 +
>>   9 files changed, 101 insertions(+), 18 deletions(-)
>>
> 


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v8 0/3] KVM: x86: Enable user wait instructions
  2019-07-19 17:18   ` Paolo Bonzini
@ 2019-07-20  7:14     ` Tao Xu
  2019-09-16  1:28     ` Tao Xu
  1 sibling, 0 replies; 9+ messages in thread
From: Tao Xu @ 2019-07-20  7:14 UTC (permalink / raw)
  To: Paolo Bonzini, rkrcmar, sean.j.christopherson, corbet, tglx,
	mingo, bp, hpa
  Cc: kvm, linux-kernel, fenghua.yu, xiaoyao.li, jingqi.liu

On 7/20/2019 1:18 AM, Paolo Bonzini wrote:
> On 19/07/19 08:31, Tao Xu wrote:
>> Ping for comments :)
> 
> Hi, I'll look at it for 5.4, right after the merge window.
> 
> Paolo
> 
Thank you Paolo!

>> On 7/16/2019 2:55 PM, Tao Xu wrote:
>>> UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions.
>>>
>>> UMONITOR arms address monitoring hardware using an address. A store
>>> to an address within the specified address range triggers the
>>> monitoring hardware to wake up the processor waiting in umwait.
>>>
>>> UMWAIT instructs the processor to enter an implementation-dependent
>>> optimized state while monitoring a range of addresses. The optimized
>>> state may be either a light-weight power/performance optimized state
>>> (c0.1 state) or an improved power/performance optimized state
>>> (c0.2 state).
>>>
>>> TPAUSE instructs the processor to enter an implementation-dependent
>>> optimized state c0.1 or c0.2 state and wake up when time-stamp counter
>>> reaches specified timeout.
>>>
>>> Availability of the user wait instructions is indicated by the presence
>>> of the CPUID feature flag WAITPKG CPUID.0x07.0x0:ECX[5].
>>>
>>> The patches enable the umonitor, umwait and tpause features in KVM.
>>> Because umwait and tpause can put a (psysical) CPU into a power saving
>>> state, by default we dont't expose it to kvm and enable it only when
>>> guest CPUID has it. If the instruction causes a delay, the amount
>>> of time delayed is called here the physical delay. The physical delay is
>>> first computed by determining the virtual delay (the time to delay
>>> relative to the VM’s timestamp counter).
>>>
>>> The release document ref below link:
>>> Intel 64 and IA-32 Architectures Software Developer's Manual,
>>> https://software.intel.com/sites/default/files/\
>>> managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf
>>>
>>> Changelog:
>>> v8:
>>>      Add vmx_waitpkg_supported() helper (Sean)
>>>      Add an accessor to expose umwait_control_cached (Sean)
>>>      Set msr_ia32_umwait_control in vcpu_vmx u32 and raise #GP when
>>>      [63:32] is set when rdmsr. (Sean)
>>>      Introduce a common exit helper handle_unexpected_vmexit (Sean)
>>> v7:
>>>      Add nested support for user wait instructions (Paolo)
>>>      Use the test on vmx->secondary_exec_control to replace
>>>      guest_cpuid_has (Paolo)
>>> v6:
>>>      add check msr_info->host_initiated in get/set msr(Xiaoyao)
>>>      restore the atomic_switch_umwait_control_msr()(Xiaoyao)
>>>
>>> Tao Xu (3):
>>>     KVM: x86: Add support for user wait instructions
>>>     KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL
>>>     KVM: vmx: Introduce handle_unexpected_vmexit and handle WAITPKG vmexit
>>>
>>>    arch/x86/include/asm/vmx.h      |  1 +
>>>    arch/x86/include/uapi/asm/vmx.h |  6 ++-
>>>    arch/x86/kernel/cpu/umwait.c    |  6 +++
>>>    arch/x86/kvm/cpuid.c            |  2 +-
>>>    arch/x86/kvm/vmx/capabilities.h |  6 +++
>>>    arch/x86/kvm/vmx/nested.c       |  5 ++
>>>    arch/x86/kvm/vmx/vmx.c          | 83 ++++++++++++++++++++++++++-------
>>>    arch/x86/kvm/vmx/vmx.h          |  9 ++++
>>>    arch/x86/kvm/x86.c              |  1 +
>>>    9 files changed, 101 insertions(+), 18 deletions(-)
>>>
>>
> 


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v8 0/3] KVM: x86: Enable user wait instructions
  2019-07-19 17:18   ` Paolo Bonzini
  2019-07-20  7:14     ` Tao Xu
@ 2019-09-16  1:28     ` Tao Xu
  2019-09-17 17:05       ` Paolo Bonzini
  1 sibling, 1 reply; 9+ messages in thread
From: Tao Xu @ 2019-09-16  1:28 UTC (permalink / raw)
  To: Paolo Bonzini, rkrcmar, sean.j.christopherson, corbet, tglx,
	mingo, bp, hpa
  Cc: kvm, linux-kernel, jingqi.liu

On 7/20/2019 1:18 AM, Paolo Bonzini wrote:
> On 19/07/19 08:31, Tao Xu wrote:
>> Ping for comments :)
> 
> Hi, I'll look at it for 5.4, right after the merge window.
> 
> Paolo
> 
Hi paolo,

Linux 5.3 has released, could you review these patches. Thank you very much!

Tao
>> On 7/16/2019 2:55 PM, Tao Xu wrote:
>>> UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions.
>>>
>>> UMONITOR arms address monitoring hardware using an address. A store
>>> to an address within the specified address range triggers the
>>> monitoring hardware to wake up the processor waiting in umwait.
>>>
>>> UMWAIT instructs the processor to enter an implementation-dependent
>>> optimized state while monitoring a range of addresses. The optimized
>>> state may be either a light-weight power/performance optimized state
>>> (c0.1 state) or an improved power/performance optimized state
>>> (c0.2 state).
>>>
>>> TPAUSE instructs the processor to enter an implementation-dependent
>>> optimized state c0.1 or c0.2 state and wake up when time-stamp counter
>>> reaches specified timeout.
>>>
>>> Availability of the user wait instructions is indicated by the presence
>>> of the CPUID feature flag WAITPKG CPUID.0x07.0x0:ECX[5].
>>>
>>> The patches enable the umonitor, umwait and tpause features in KVM.
>>> Because umwait and tpause can put a (psysical) CPU into a power saving
>>> state, by default we dont't expose it to kvm and enable it only when
>>> guest CPUID has it. If the instruction causes a delay, the amount
>>> of time delayed is called here the physical delay. The physical delay is
>>> first computed by determining the virtual delay (the time to delay
>>> relative to the VM’s timestamp counter).
>>>
>>> The release document ref below link:
>>> Intel 64 and IA-32 Architectures Software Developer's Manual,
>>> https://software.intel.com/sites/default/files/\
>>> managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf
>>>
>>> Changelog:
>>> v8:
>>>      Add vmx_waitpkg_supported() helper (Sean)
>>>      Add an accessor to expose umwait_control_cached (Sean)
>>>      Set msr_ia32_umwait_control in vcpu_vmx u32 and raise #GP when
>>>      [63:32] is set when rdmsr. (Sean)
>>>      Introduce a common exit helper handle_unexpected_vmexit (Sean)
>>> v7:
>>>      Add nested support for user wait instructions (Paolo)
>>>      Use the test on vmx->secondary_exec_control to replace
>>>      guest_cpuid_has (Paolo)
>>> v6:
>>>      add check msr_info->host_initiated in get/set msr(Xiaoyao)
>>>      restore the atomic_switch_umwait_control_msr()(Xiaoyao)
>>>
>>> Tao Xu (3):
>>>     KVM: x86: Add support for user wait instructions
>>>     KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL
>>>     KVM: vmx: Introduce handle_unexpected_vmexit and handle WAITPKG vmexit
>>>
>>>    arch/x86/include/asm/vmx.h      |  1 +
>>>    arch/x86/include/uapi/asm/vmx.h |  6 ++-
>>>    arch/x86/kernel/cpu/umwait.c    |  6 +++
>>>    arch/x86/kvm/cpuid.c            |  2 +-
>>>    arch/x86/kvm/vmx/capabilities.h |  6 +++
>>>    arch/x86/kvm/vmx/nested.c       |  5 ++
>>>    arch/x86/kvm/vmx/vmx.c          | 83 ++++++++++++++++++++++++++-------
>>>    arch/x86/kvm/vmx/vmx.h          |  9 ++++
>>>    arch/x86/kvm/x86.c              |  1 +
>>>    9 files changed, 101 insertions(+), 18 deletions(-)
>>>
>>
> 


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v8 0/3] KVM: x86: Enable user wait instructions
  2019-09-16  1:28     ` Tao Xu
@ 2019-09-17 17:05       ` Paolo Bonzini
  0 siblings, 0 replies; 9+ messages in thread
From: Paolo Bonzini @ 2019-09-17 17:05 UTC (permalink / raw)
  To: Tao Xu, rkrcmar, sean.j.christopherson, corbet, tglx, mingo, bp, hpa
  Cc: kvm, linux-kernel, jingqi.liu

On 16/09/19 03:28, Tao Xu wrote:
> On 7/20/2019 1:18 AM, Paolo Bonzini wrote:
>> On 19/07/19 08:31, Tao Xu wrote:
>>> Ping for comments :)
>>
>> Hi, I'll look at it for 5.4, right after the merge window.
>>
>> Paolo
>>
> Hi paolo,
> 
> Linux 5.3 has released, could you review these patches. Thank you very
> much!
> 
> Tao
>>> On 7/16/2019 2:55 PM, Tao Xu wrote:
>>>> UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions.
>>>>
>>>> UMONITOR arms address monitoring hardware using an address. A store
>>>> to an address within the specified address range triggers the
>>>> monitoring hardware to wake up the processor waiting in umwait.
>>>>
>>>> UMWAIT instructs the processor to enter an implementation-dependent
>>>> optimized state while monitoring a range of addresses. The optimized
>>>> state may be either a light-weight power/performance optimized state
>>>> (c0.1 state) or an improved power/performance optimized state
>>>> (c0.2 state).
>>>>
>>>> TPAUSE instructs the processor to enter an implementation-dependent
>>>> optimized state c0.1 or c0.2 state and wake up when time-stamp counter
>>>> reaches specified timeout.
>>>>
>>>> Availability of the user wait instructions is indicated by the presence
>>>> of the CPUID feature flag WAITPKG CPUID.0x07.0x0:ECX[5].
>>>>
>>>> The patches enable the umonitor, umwait and tpause features in KVM.
>>>> Because umwait and tpause can put a (psysical) CPU into a power saving
>>>> state, by default we dont't expose it to kvm and enable it only when
>>>> guest CPUID has it. If the instruction causes a delay, the amount
>>>> of time delayed is called here the physical delay. The physical
>>>> delay is
>>>> first computed by determining the virtual delay (the time to delay
>>>> relative to the VM’s timestamp counter).
>>>>
>>>> The release document ref below link:
>>>> Intel 64 and IA-32 Architectures Software Developer's Manual,
>>>> https://software.intel.com/sites/default/files/\
>>>> managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf
>>>>
>>>> Changelog:
>>>> v8:
>>>>      Add vmx_waitpkg_supported() helper (Sean)
>>>>      Add an accessor to expose umwait_control_cached (Sean)
>>>>      Set msr_ia32_umwait_control in vcpu_vmx u32 and raise #GP when
>>>>      [63:32] is set when rdmsr. (Sean)
>>>>      Introduce a common exit helper handle_unexpected_vmexit (Sean)
>>>> v7:
>>>>      Add nested support for user wait instructions (Paolo)
>>>>      Use the test on vmx->secondary_exec_control to replace
>>>>      guest_cpuid_has (Paolo)
>>>> v6:
>>>>      add check msr_info->host_initiated in get/set msr(Xiaoyao)
>>>>      restore the atomic_switch_umwait_control_msr()(Xiaoyao)
>>>>
>>>> Tao Xu (3):
>>>>     KVM: x86: Add support for user wait instructions
>>>>     KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL
>>>>     KVM: vmx: Introduce handle_unexpected_vmexit and handle WAITPKG
>>>> vmexit
>>>>
>>>>    arch/x86/include/asm/vmx.h      |  1 +
>>>>    arch/x86/include/uapi/asm/vmx.h |  6 ++-
>>>>    arch/x86/kernel/cpu/umwait.c    |  6 +++
>>>>    arch/x86/kvm/cpuid.c            |  2 +-
>>>>    arch/x86/kvm/vmx/capabilities.h |  6 +++
>>>>    arch/x86/kvm/vmx/nested.c       |  5 ++
>>>>    arch/x86/kvm/vmx/vmx.c          | 83
>>>> ++++++++++++++++++++++++++-------
>>>>    arch/x86/kvm/vmx/vmx.h          |  9 ++++
>>>>    arch/x86/kvm/x86.c              |  1 +
>>>>    9 files changed, 101 insertions(+), 18 deletions(-)
>>>>
>>>
>>
> 

Queued, thanks.

Paolo

^ permalink raw reply	[flat|nested] 9+ messages in thread

end of thread, back to index

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-07-16  6:55 [PATCH v8 0/3] KVM: x86: Enable user wait instructions Tao Xu
2019-07-16  6:55 ` [PATCH v8 1/3] KVM: x86: Add support for " Tao Xu
2019-07-16  6:55 ` [PATCH v8 2/3] KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL Tao Xu
2019-07-16  6:55 ` [PATCH v8 3/3] KVM: vmx: Introduce handle_unexpected_vmexit and handle WAITPKG vmexit Tao Xu
2019-07-19  6:31 ` [PATCH v8 0/3] KVM: x86: Enable user wait instructions Tao Xu
2019-07-19 17:18   ` Paolo Bonzini
2019-07-20  7:14     ` Tao Xu
2019-09-16  1:28     ` Tao Xu
2019-09-17 17:05       ` Paolo Bonzini

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