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From:   Sean Christopherson <sean.j.christopherson@intel.com>
To:     "Singh, Brijesh" <brijesh.singh@amd.com>
Cc:     Liran Alon <liran.alon@oracle.com>,
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Subject: Re: [PATCH 1/2] KVM: SVM: Fix workaround for AMD Errata 1096
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On Tue, Jul 16, 2019 at 08:02:43PM +0000, Singh, Brijesh wrote:
> 
> On 7/16/19 2:34 PM, Liran Alon wrote:
> > Why CPU needs to be at CPL3?
> > The requirement for SMAP should be that this page is user-accessible in guest page-tables.
> > Think on a case where guest have CR4.SMAP=1 and CR4.SMEP=0.
> > 
> 
> We are discussing reserved NPF so we need to be at CPL3.

For my own education, why does reserved NPF require CPL3?  I.e. what
happens if a reserved bit is encountered at CPL<3 (or do they simply not
exist)?