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Mon, 29 Jul 2019 11:56:19 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K CC: Daniel Lezcano , Thomas Gleixner , Atish Patra , Alistair Francis , Damien Le Moal , Christoph Hellwig , Anup Patel , "kvm@vger.kernel.org" , "linux-riscv@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Anup Patel Subject: [RFC PATCH 00/16] KVM RISC-V Support Thread-Topic: [RFC PATCH 00/16] KVM RISC-V Support Thread-Index: AQHVRgSiwwiv+vb1mEmL735Or1vKMg== Date: Mon, 29 Jul 2019 11:56:19 +0000 Message-ID: <20190729115544.17895-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: PN1PR01CA0116.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00::32) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [106.51.23.101] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 325ef1f5-8903-4ed5-2b12-08d7141bc45f x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:MN2PR04MB5952; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 325ef1f5-8903-4ed5-2b12-08d7141bc45f X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Jul 2019 11:56:19.1595 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Anup.Patel@wdc.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB5952 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This series adds initial KVM RISC-V support. Currently, we are able to boot RISC-V 64bit Linux Guests with multiple VCPUs. Few key aspects of KVM RISC-V added by this series are: 1. Minimal possible KVM world-switch which touches only GPRs and few CSRs. 2. Full Guest/VM switch is done via vcpu_get/vcpu_put infrastructure. 3. KVM ONE_REG interface for VCPU register access from user-space. 4. PLIC emulation is done in user-space. In-kernel PLIC emulation, will be added in future. 5. Timer and IPI emuation is done in-kernel. 6. MMU notifiers supported. 7. FP lazy save/restore supported. 8. SBI v0.1 emulation for KVM Guest available. More feature additions and enhancments will follow after this series and eventually KVM RISC-V will be at-par with other architectures. This series is based upon KVM pre-patches sent by Atish earlier (https://lkml.org/lkml/2019/7/26/1271) and it can be found in riscv_kvm_v1 branch at: https//github.com/avpatel/linux.git Our work-in-progress KVMTOOL RISC-V port can be found in riscv_v1 branch at= : https//github.com/avpatel/kvmtool.git We need OpenSBI with RISC-V hypervisor extension support which can be found in hyp_ext_changes_v1 branch at: https://github.com/riscv/opensbi.git The QEMU RISC-V hypervisor emulation is done by Alistair and is available in riscv-hyp-work.next branch at: https://github.com/alistair23/qemu.git To play around with KVM RISC-V, here are few reference commands: 1) To cross-compile KVMTOOL: $ make lkvm-static 2) To launch RISC-V Host Linux: $ qemu-system-riscv64 -monitor null -cpu rv64,h=3Dtrue -M virt \ -m 512M -display none -serial mon:stdio \ -kernel opensbi/build/platform/qemu/virt/firmware/fw_jump.elf \ -device loader,file=3Dbuild-riscv64/arch/riscv/boot/Image,addr=3D0x80200= 000 \ -initrd ./rootfs_kvm_riscv64.img \ -append "root=3D/dev/ram rw console=3DttyS0 earlycon=3Dsbi" 3) To launch RISC-V Guest Linux with 9P rootfs: $ ./apps/lkvm-static run -m 128 -c2 --console serial \ -p "console=3DttyS0 earlycon=3Duart8250,mmio,0x3f8" -k ./apps/Image --de= bug 4) To launch RISC-V Guest Linux with initrd: $ ./apps/lkvm-static run -m 128 -c2 --console serial \ -p "console=3DttyS0 earlycon=3Duart8250,mmio,0x3f8" -k ./apps/Image \ -i ./apps/rootfs.img --debug Anup Patel (13): KVM: RISC-V: Add KVM_REG_RISCV for ONE_REG interface RISC-V: Add hypervisor extension related CSR defines RISC-V: Add initial skeletal KVM support RISC-V: KVM: Implement VCPU create, init and destroy functions RISC-V: KVM: Implement VCPU interrupts and requests handling RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls RISC-V: KVM: Implement VCPU world-switch RISC-V: KVM: Handle MMIO exits for VCPU RISC-V: KVM: Handle WFI exits for VCPU RISC-V: KVM: Implement VMID allocator RISC-V: KVM: Implement stage2 page table programming RISC-V: KVM: Implement MMU notifiers RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfig Atish Patra (3): RISC-V: KVM: Add timer functionality RISC-V: KVM: FP lazy save/restore RISC-V: KVM: Add SBI v0.1 support arch/riscv/Kconfig | 2 + arch/riscv/Makefile | 2 + arch/riscv/configs/defconfig | 23 +- arch/riscv/configs/rv32_defconfig | 13 + arch/riscv/include/asm/csr.h | 58 ++ arch/riscv/include/asm/kvm_host.h | 232 ++++++ arch/riscv/include/asm/kvm_vcpu_timer.h | 32 + arch/riscv/include/asm/pgtable-bits.h | 1 + arch/riscv/include/uapi/asm/kvm.h | 74 ++ arch/riscv/kernel/asm-offsets.c | 148 ++++ arch/riscv/kvm/Kconfig | 34 + arch/riscv/kvm/Makefile | 14 + arch/riscv/kvm/main.c | 64 ++ arch/riscv/kvm/mmu.c | 904 ++++++++++++++++++++++++ arch/riscv/kvm/tlb.S | 42 ++ arch/riscv/kvm/vcpu.c | 817 +++++++++++++++++++++ arch/riscv/kvm/vcpu_exit.c | 553 +++++++++++++++ arch/riscv/kvm/vcpu_sbi.c | 118 ++++ arch/riscv/kvm/vcpu_switch.S | 367 ++++++++++ arch/riscv/kvm/vcpu_timer.c | 106 +++ arch/riscv/kvm/vm.c | 107 +++ arch/riscv/kvm/vmid.c | 130 ++++ drivers/clocksource/timer-riscv.c | 6 + include/clocksource/timer-riscv.h | 14 + include/uapi/linux/kvm.h | 1 + 25 files changed, 3857 insertions(+), 5 deletions(-) create mode 100644 arch/riscv/include/asm/kvm_host.h create mode 100644 arch/riscv/include/asm/kvm_vcpu_timer.h create mode 100644 arch/riscv/include/uapi/asm/kvm.h create mode 100644 arch/riscv/kvm/Kconfig create mode 100644 arch/riscv/kvm/Makefile create mode 100644 arch/riscv/kvm/main.c create mode 100644 arch/riscv/kvm/mmu.c create mode 100644 arch/riscv/kvm/tlb.S create mode 100644 arch/riscv/kvm/vcpu.c create mode 100644 arch/riscv/kvm/vcpu_exit.c create mode 100644 arch/riscv/kvm/vcpu_sbi.c create mode 100644 arch/riscv/kvm/vcpu_switch.S create mode 100644 arch/riscv/kvm/vcpu_timer.c create mode 100644 arch/riscv/kvm/vm.c create mode 100644 arch/riscv/kvm/vmid.c create mode 100644 include/clocksource/timer-riscv.h -- 2.17.1