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Mon, 23 Dec 2019 11:36:10 +0000 Received: from wdc.com (106.51.20.238) by MA1PR01CA0077.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00::17) with Microsoft SMTP Server (version=TLS1_2, cipher=) via Frontend Transport; Mon, 23 Dec 2019 11:36:05 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Albert Ou , Paolo Bonzini , Radim K CC: Alexander Graf , Atish Patra , Alistair Francis , Damien Le Moal , Christoph Hellwig , Anup Patel , "kvm@vger.kernel.org" , "kvm-riscv@lists.infradead.org" , "linux-riscv@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Anup Patel Subject: [PATCH v10 06/19] RISC-V: KVM: Implement VCPU interrupts and requests handling Thread-Topic: [PATCH v10 06/19] RISC-V: KVM: Implement VCPU interrupts and requests handling Thread-Index: AQHVuYUslzLNkMdBiUOsRkelWHGXJw== Date: Mon, 23 Dec 2019 11:36:10 +0000 Message-ID: <20191223113443.68969-7-anup.patel@wdc.com> References: <20191223113443.68969-1-anup.patel@wdc.com> In-Reply-To: <20191223113443.68969-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MA1PR01CA0077.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00::17) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; 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x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: tSIlT+WPr/IAu0GP/F54jfEtyYigGI4u2yiDXwtZreGmX4me8nYLoHaUHebVy9n9FslRuuOkrpkwrAk1werLTBPWEkqe27+uwWy+yys6kHJBGGCjcghFYI2mccbuaRiugx7Kdf3R8J4aRrZooUzQKMyKaPS3NSySUuVmJCZaUTYoVy7w0Bjbpoz1x4s2/pbdhFJNvky77G8jKMNt2AzKGFL4YRrSvTteHmPPkkSQeGeFS4P5JRgwIC2v7BYSVTMqD2OKXTy1z6Tl5RPctmtGt25RnkTxuqCZJVrJR4Uu4FU2sdhrMvRJJXJbzT49EHmXrcsdy51r11A2Am5akMvlXRssveMHQRq9ADPUCdEwaYDZDCAxWGB8NcJx0mBRNIBoQrc4plAOT9qEo/HZMGi0ND68F6tlCCilb2vvZMp1/yuC4Vp/LIsxvZUMJrclUUqPZOKv2tHlxqPNBDeYFumOceKoPFSoieuEiXBrR5zQFSr67deEyWGvN9eVPSOIAxGA Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 42f343a4-81c5-462c-ab11-08d7879c4eca X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Dec 2019 11:36:10.5775 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: X+Vzt6kBQyRg6qbVGMYxl9eTbgNVy4/W8SIsBomkm28hXWz/vaBWDaPgi+WXX2St1VgWYWG8RF2qcZKoboORow== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB7072 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This patch implements VCPU interrupts and requests which are both asynchronous events. The VCPU interrupts can be set/unset using KVM_INTERRUPT ioctl from user-space. In future, the in-kernel IRQCHIP emulation will use kvm_riscv_vcpu_set_interrupt() and kvm_riscv_vcpu_unset_interrupt() functions to set/unset VCPU interrupts. Important VCPU requests implemented by this patch are: KVM_REQ_SLEEP - set whenever VCPU itself goes to sleep state KVM_REQ_VCPU_RESET - set whenever VCPU reset is requested The WFI trap-n-emulate (added later) will use KVM_REQ_SLEEP request and kvm_riscv_vcpu_has_interrupt() function. The KVM_REQ_VCPU_RESET request will be used by SBI emulation (added later) to power-up a VCPU in power-off state. The user-space can use the GET_MPSTATE/SET_MPSTATE ioctls to get/set power state of a VCPU. Signed-off-by: Anup Patel Acked-by: Paolo Bonzini Reviewed-by: Paolo Bonzini Reviewed-by: Alexander Graf --- arch/riscv/include/asm/kvm_host.h | 23 ++++ arch/riscv/include/uapi/asm/kvm.h | 3 + arch/riscv/kvm/vcpu.c | 182 +++++++++++++++++++++++++++--- 3 files changed, 195 insertions(+), 13 deletions(-) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm= _host.h index 297431660be6..94ae81220ac6 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -122,6 +122,21 @@ struct kvm_vcpu_arch { /* CPU CSR context upon Guest VCPU reset */ struct kvm_vcpu_csr guest_reset_csr; =20 + /* + * VCPU interrupts + * + * We have a lockless approach for tracking pending VCPU interrupts + * implemented using atomic bitops. The irqs_pending bitmap represent + * pending interrupts whereas irqs_pending_mask represent bits changed + * in irqs_pending. Our approach is modeled around multiple producer + * and single consumer problem where the consumer is the VCPU itself. + */ + unsigned long irqs_pending; + unsigned long irqs_pending_mask; + + /* VCPU power-off state */ + bool power_off; + /* Don't run the VCPU (blocked) */ bool pause; =20 @@ -147,4 +162,12 @@ int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct = kvm_run *run, =20 static inline void __kvm_riscv_switch_to(struct kvm_vcpu_arch *vcpu_arch) = {} =20 +int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq); +int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq= ); +void kvm_riscv_vcpu_flush_interrupts(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu); +bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, unsigned long ma= sk); +void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu); + #endif /* __RISCV_KVM_HOST_H__ */ diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index d15875818b6e..6dbc056d58ba 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -18,6 +18,9 @@ =20 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 =20 +#define KVM_INTERRUPT_SET -1U +#define KVM_INTERRUPT_UNSET -2U + /* for KVM_GET_REGS and KVM_SET_REGS */ struct kvm_regs { }; diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index cf8ca8d4a9ea..989f2be83c19 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -50,6 +51,9 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) memcpy(csr, reset_csr, sizeof(*csr)); =20 memcpy(cntx, reset_cntx, sizeof(*cntx)); + + WRITE_ONCE(vcpu->arch.irqs_pending, 0); + WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0); } =20 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id) @@ -116,8 +120,7 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) =20 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) { - /* TODO: */ - return 0; + return kvm_riscv_vcpu_has_interrupts(vcpu, 1UL << IRQ_VS_TIMER); } =20 void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) @@ -130,20 +133,18 @@ void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) =20 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) { - /* TODO: */ - return 0; + return (kvm_riscv_vcpu_has_interrupts(vcpu, -1UL) && + !vcpu->arch.power_off && !vcpu->arch.pause); } =20 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) { - /* TODO: */ - return 0; + return kvm_vcpu_exiting_guest_mode(vcpu) =3D=3D IN_GUEST_MODE; } =20 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) { - /* TODO: */ - return false; + return (vcpu->arch.guest_context.sstatus & SR_SPP) ? true : false; } =20 bool kvm_arch_has_vcpu_debugfs(void) @@ -164,7 +165,21 @@ vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, = struct vm_fault *vmf) long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) { - /* TODO; */ + struct kvm_vcpu *vcpu =3D filp->private_data; + void __user *argp =3D (void __user *)arg; + + if (ioctl =3D=3D KVM_INTERRUPT) { + struct kvm_interrupt irq; + + if (copy_from_user(&irq, argp, sizeof(irq))) + return -EFAULT; + + if (irq.irq =3D=3D KVM_INTERRUPT_SET) + return kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_VS_EXT); + else + return kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_VS_EXT); + } + return -ENOIOCTLCMD; } =20 @@ -213,18 +228,121 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vc= pu, struct kvm_regs *regs) return -EINVAL; } =20 +void kvm_riscv_vcpu_flush_interrupts(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_csr *csr =3D &vcpu->arch.guest_csr; + unsigned long mask, val; + + if (READ_ONCE(vcpu->arch.irqs_pending_mask)) { + mask =3D xchg_acquire(&vcpu->arch.irqs_pending_mask, 0); + val =3D READ_ONCE(vcpu->arch.irqs_pending) & mask; + + csr->hip &=3D ~mask; + csr->hip |=3D val; + } +} + +void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu) +{ + unsigned long hip; + struct kvm_vcpu_arch *v =3D &vcpu->arch; + struct kvm_vcpu_csr *csr =3D &vcpu->arch.guest_csr; + + /* Read current HIP and HIE CSRs */ + hip =3D csr_read(CSR_HIP); + csr->hie =3D csr_read(CSR_HIE); + + /* Sync-up HIP.VSSIP bit changes does by Guest */ + if ((csr->hip ^ hip) & (1UL << IRQ_VS_SOFT)) { + if (hip & (1UL << IRQ_VS_SOFT)) { + if (!test_and_set_bit(IRQ_VS_SOFT, + &v->irqs_pending_mask)) + set_bit(IRQ_VS_SOFT, &v->irqs_pending); + } else { + if (!test_and_set_bit(IRQ_VS_SOFT, + &v->irqs_pending_mask)) + clear_bit(IRQ_VS_SOFT, &v->irqs_pending); + } + } +} + +int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) +{ + if (irq !=3D IRQ_VS_SOFT && + irq !=3D IRQ_VS_TIMER && + irq !=3D IRQ_VS_EXT) + return -EINVAL; + + set_bit(irq, &vcpu->arch.irqs_pending); + smp_mb__before_atomic(); + set_bit(irq, &vcpu->arch.irqs_pending_mask); + + kvm_vcpu_kick(vcpu); + + return 0; +} + +int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq= ) +{ + if (irq !=3D IRQ_VS_SOFT && + irq !=3D IRQ_VS_TIMER && + irq !=3D IRQ_VS_EXT) + return -EINVAL; + + clear_bit(irq, &vcpu->arch.irqs_pending); + smp_mb__before_atomic(); + set_bit(irq, &vcpu->arch.irqs_pending_mask); + + return 0; +} + +bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, unsigned long ma= sk) +{ + return (READ_ONCE(vcpu->arch.irqs_pending) & + vcpu->arch.guest_csr.hie & mask) ? true : false; +} + +void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu) +{ + vcpu->arch.power_off =3D true; + kvm_make_request(KVM_REQ_SLEEP, vcpu); + kvm_vcpu_kick(vcpu); +} + +void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu) +{ + vcpu->arch.power_off =3D false; + kvm_vcpu_wake_up(vcpu); +} + int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, struct kvm_mp_state *mp_state) { - /* TODO: */ + if (vcpu->arch.power_off) + mp_state->mp_state =3D KVM_MP_STATE_STOPPED; + else + mp_state->mp_state =3D KVM_MP_STATE_RUNNABLE; + return 0; } =20 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, struct kvm_mp_state *mp_state) { - /* TODO: */ - return 0; + int ret =3D 0; + + switch (mp_state->mp_state) { + case KVM_MP_STATE_RUNNABLE: + vcpu->arch.power_off =3D false; + break; + case KVM_MP_STATE_STOPPED: + kvm_riscv_vcpu_power_off(vcpu); + break; + default: + ret =3D -EINVAL; + } + + return ret; } =20 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, @@ -248,7 +366,33 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) =20 static void kvm_riscv_check_vcpu_requests(struct kvm_vcpu *vcpu) { - /* TODO: */ + struct swait_queue_head *wq =3D kvm_arch_vcpu_wq(vcpu); + + if (kvm_request_pending(vcpu)) { + if (kvm_check_request(KVM_REQ_SLEEP, vcpu)) { + swait_event_interruptible_exclusive(*wq, + ((!vcpu->arch.power_off) && + (!vcpu->arch.pause))); + + if (vcpu->arch.power_off || vcpu->arch.pause) { + /* + * Awaken to handle a signal, request to + * sleep again later. + */ + kvm_make_request(KVM_REQ_SLEEP, vcpu); + } + } + + if (kvm_check_request(KVM_REQ_VCPU_RESET, vcpu)) + kvm_riscv_reset_vcpu(vcpu); + } +} + +static void kvm_riscv_update_hip(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_csr *csr =3D &vcpu->arch.guest_csr; + + csr_write(CSR_HIP, csr->hip); } =20 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) @@ -311,6 +455,15 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, str= uct kvm_run *run) srcu_read_unlock(&vcpu->kvm->srcu, vcpu->arch.srcu_idx); smp_mb__after_srcu_read_unlock(); =20 + /* + * We might have got VCPU interrupts updated asynchronously + * so update it in HW. + */ + kvm_riscv_vcpu_flush_interrupts(vcpu); + + /* Update HIP CSR for current CPU */ + kvm_riscv_update_hip(vcpu); + if (ret <=3D 0 || kvm_request_pending(vcpu)) { vcpu->mode =3D OUTSIDE_GUEST_MODE; @@ -337,6 +490,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, stru= ct kvm_run *run) htval =3D csr_read(CSR_HTVAL); htinst =3D csr_read(CSR_HTINST); =20 + /* Syncup interrupts state with HW */ + kvm_riscv_vcpu_sync_interrupts(vcpu); + /* * We may have taken a host interrupt in VS/VU-mode (i.e. * while executing the guest). This interrupt is still --=20 2.17.1