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Mon, 27 Jan 2020 12:36:35 +0000 Received: from wdc.com (49.207.48.168) by MA1PR01CA0095.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:1::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2665.22 via Frontend Transport; Mon, 27 Jan 2020 12:36:32 +0000 From: Anup Patel To: Will Deacon CC: Paolo Bonzini , Atish Patra , Alistair Francis , Anup Patel , "kvm@vger.kernel.org" , "kvm-riscv@lists.infradead.org" , Anup Patel Subject: [kvmtool RFC PATCH v2 8/8] riscv: Generate PCI host DT node Thread-Topic: [kvmtool RFC PATCH v2 8/8] riscv: Generate PCI host DT node Thread-Index: AQHV1Q5pc9nInC2qUkaALyDT8Pfpcw== Date: Mon, 27 Jan 2020 12:36:35 +0000 Message-ID: <20200127123527.106825-9-anup.patel@wdc.com> References: <20200127123527.106825-1-anup.patel@wdc.com> In-Reply-To: <20200127123527.106825-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MA1PR01CA0095.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:1::11) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; 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Of course, PCI host for Guest/VM is not useful at the moment because it's mostly for PCI pass-through and we don't have IOMMU and interrupt routing available for KVM RISC-V. In future, we might be able to use PCI host for VirtIO PCI transport or other software emulated PCI devices. Signed-off-by: Anup Patel --- Makefile | 1 + riscv/fdt.c | 3 + riscv/include/kvm/kvm-arch.h | 2 + riscv/pci.c | 109 +++++++++++++++++++++++++++++++++++ 4 files changed, 115 insertions(+) create mode 100644 riscv/pci.c diff --git a/Makefile b/Makefile index fb78fa2..fa5e4f7 100644 --- a/Makefile +++ b/Makefile @@ -201,6 +201,7 @@ ifeq ($(ARCH),riscv) OBJS +=3D riscv/irq.o OBJS +=3D riscv/kvm.o OBJS +=3D riscv/kvm-cpu.o + OBJS +=3D riscv/pci.o OBJS +=3D riscv/plic.o =20 ARCH_WANT_LIBFDT :=3D y diff --git a/riscv/fdt.c b/riscv/fdt.c index 3b56e30..fc8aa88 100644 --- a/riscv/fdt.c +++ b/riscv/fdt.c @@ -167,6 +167,9 @@ static int setup_fdt(struct kvm *kvm) dev_hdr =3D device__next_dev(dev_hdr); } =20 + /* PCI host controller */ + pci__generate_fdt_nodes(fdt); + _FDT(fdt_end_node(fdt)); =20 if (fdt_stdout_path) { diff --git a/riscv/include/kvm/kvm-arch.h b/riscv/include/kvm/kvm-arch.h index 630cd6b..bc66e3b 100644 --- a/riscv/include/kvm/kvm-arch.h +++ b/riscv/include/kvm/kvm-arch.h @@ -80,4 +80,6 @@ void plic__generate_irq_prop(void *fdt, u8 irq, enum irq_= type irq_type); =20 void plic__irq_trig(struct kvm *kvm, int irq, int level, bool edge); =20 +void pci__generate_fdt_nodes(void *fdt); + #endif /* KVM__KVM_ARCH_H */ diff --git a/riscv/pci.c b/riscv/pci.c new file mode 100644 index 0000000..666a452 --- /dev/null +++ b/riscv/pci.c @@ -0,0 +1,109 @@ +#include "kvm/devices.h" +#include "kvm/fdt.h" +#include "kvm/kvm.h" +#include "kvm/of_pci.h" +#include "kvm/pci.h" +#include "kvm/util.h" + +/* + * An entry in the interrupt-map table looks like: + * + */ + +struct of_interrupt_map_entry { + struct of_pci_irq_mask pci_irq_mask; + u32 plic_phandle; + u32 plic_irq; +} __attribute__((packed)); + +void pci__generate_fdt_nodes(void *fdt) +{ + struct device_header *dev_hdr; + struct of_interrupt_map_entry irq_map[OF_PCI_IRQ_MAP_MAX]; + unsigned nentries =3D 0; + /* Bus range */ + u32 bus_range[] =3D { cpu_to_fdt32(0), cpu_to_fdt32(1), }; + /* Configuration Space */ + u64 cfg_reg_prop[] =3D { cpu_to_fdt64(KVM_PCI_CFG_AREA), + cpu_to_fdt64(RISCV_PCI_CFG_SIZE), }; + /* Describe the memory ranges */ + struct of_pci_ranges_entry ranges[] =3D { + { + .pci_addr =3D { + .hi =3D cpu_to_fdt32(of_pci_b_ss(OF_PCI_SS_IO)), + .mid =3D 0, + .lo =3D 0, + }, + .cpu_addr =3D cpu_to_fdt64(KVM_IOPORT_AREA), + .length =3D cpu_to_fdt64(RISCV_IOPORT_SIZE), + }, + { + .pci_addr =3D { + .hi =3D cpu_to_fdt32(of_pci_b_ss(OF_PCI_SS_M32)), + .mid =3D cpu_to_fdt32(KVM_PCI_MMIO_AREA >> 32), + .lo =3D cpu_to_fdt32(KVM_PCI_MMIO_AREA), + }, + .cpu_addr =3D cpu_to_fdt64(KVM_PCI_MMIO_AREA), + .length =3D cpu_to_fdt64(RISCV_PCI_MMIO_SIZE), + }, + }; + + /* Boilerplate PCI properties */ + _FDT(fdt_begin_node(fdt, "pci")); + _FDT(fdt_property_string(fdt, "device_type", "pci")); + _FDT(fdt_property_cell(fdt, "#address-cells", 0x3)); + _FDT(fdt_property_cell(fdt, "#size-cells", 0x2)); + _FDT(fdt_property_cell(fdt, "#interrupt-cells", 0x1)); + _FDT(fdt_property_string(fdt, "compatible", "pci-host-cam-generic")); + _FDT(fdt_property(fdt, "dma-coherent", NULL, 0)); + + _FDT(fdt_property(fdt, "bus-range", bus_range, sizeof(bus_range))); + _FDT(fdt_property(fdt, "reg", &cfg_reg_prop, sizeof(cfg_reg_prop))); + _FDT(fdt_property(fdt, "ranges", ranges, sizeof(ranges))); + + /* Generate the interrupt map ... */ + dev_hdr =3D device__first_dev(DEVICE_BUS_PCI); + while (dev_hdr && nentries < ARRAY_SIZE(irq_map)) { + struct of_interrupt_map_entry *entry =3D &irq_map[nentries]; + struct pci_device_header *pci_hdr =3D dev_hdr->data; + u8 dev_num =3D dev_hdr->dev_num; + u8 pin =3D pci_hdr->irq_pin; + u8 irq =3D pci_hdr->irq_line; + + *entry =3D (struct of_interrupt_map_entry) { + .pci_irq_mask =3D { + .pci_addr =3D { + .hi =3D cpu_to_fdt32(of_pci_b_ddddd(dev_num)), + .mid =3D 0, + .lo =3D 0, + }, + .pci_pin =3D cpu_to_fdt32(pin), + }, + .plic_phandle =3D cpu_to_fdt32(PHANDLE_PLIC), + .plic_irq =3D cpu_to_fdt32(irq), + }; + + nentries++; + dev_hdr =3D device__next_dev(dev_hdr); + } + + _FDT(fdt_property(fdt, "interrupt-map", irq_map, + sizeof(struct of_interrupt_map_entry) * nentries)); + + /* ... and the corresponding mask. */ + if (nentries) { + struct of_pci_irq_mask irq_mask =3D { + .pci_addr =3D { + .hi =3D cpu_to_fdt32(of_pci_b_ddddd(-1)), + .mid =3D 0, + .lo =3D 0, + }, + .pci_pin =3D cpu_to_fdt32(7), + }; + + _FDT(fdt_property(fdt, "interrupt-map-mask", &irq_mask, + sizeof(irq_mask))); + } + + _FDT(fdt_end_node(fdt)); +} --=20 2.17.1