From: Sean Christopherson <sean.j.christopherson@intel.com>
To: Xiaoyao Li <xiaoyao.li@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
hpa@zytor.com, Paolo Bonzini <pbonzini@redhat.com>,
Andy Lutomirski <luto@kernel.org>,
tony.luck@intel.com, peterz@infradead.org, fenghua.yu@intel.com,
x86@kernel.org, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 3/8] x86/split_lock: Cache the value of MSR_TEST_CTRL in percpu data
Date: Tue, 3 Mar 2020 11:18:33 -0800 [thread overview]
Message-ID: <20200303191833.GT1439@linux.intel.com> (raw)
In-Reply-To: <20200206070412.17400-4-xiaoyao.li@intel.com>
On Thu, Feb 06, 2020 at 03:04:07PM +0800, Xiaoyao Li wrote:
> Cache the value of MSR_TEST_CTRL in percpu data msr_test_ctrl_cache,
> which will be used by KVM module.
>
> It also avoids an expensive RDMSR instruction if SLD needs to be context
> switched.
>
> Suggested-by: Sean Christopherson <sean.j.christopherson@intel.com>
> Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
> ---
> arch/x86/include/asm/cpu.h | 2 ++
> arch/x86/kernel/cpu/intel.c | 19 ++++++++++++-------
> 2 files changed, 14 insertions(+), 7 deletions(-)
>
> diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
> index ff567afa6ee1..2b20829db450 100644
> --- a/arch/x86/include/asm/cpu.h
> +++ b/arch/x86/include/asm/cpu.h
> @@ -27,6 +27,8 @@ struct x86_cpu {
> };
>
> #ifdef CONFIG_HOTPLUG_CPU
> +DECLARE_PER_CPU(u64, msr_test_ctrl_cache);
> +
> extern int arch_register_cpu(int num);
> extern void arch_unregister_cpu(int);
> extern void start_cpu0(void);
> diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
> index 49535ed81c22..ff27d026cb4a 100644
> --- a/arch/x86/kernel/cpu/intel.c
> +++ b/arch/x86/kernel/cpu/intel.c
> @@ -46,6 +46,9 @@ enum split_lock_detect_state {
> */
> static enum split_lock_detect_state sld_state = sld_off;
>
> +DEFINE_PER_CPU(u64, msr_test_ctrl_cache);
> +EXPORT_PER_CPU_SYMBOL_GPL(msr_test_ctrl_cache);
> +
> /*
> * Processors which have self-snooping capability can handle conflicting
> * memory type across CPUs by snooping its own cache. However, there exists
> @@ -1043,20 +1046,22 @@ static void __init split_lock_setup(void)
> */
> static void __sld_msr_set(bool on)
> {
> - u64 test_ctrl_val;
> -
> - rdmsrl(MSR_TEST_CTRL, test_ctrl_val);
> -
> if (on)
> - test_ctrl_val |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
> + this_cpu_or(msr_test_ctrl_cache, MSR_TEST_CTRL_SPLIT_LOCK_DETECT);
> else
> - test_ctrl_val &= ~MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
> + this_cpu_and(msr_test_ctrl_cache, ~MSR_TEST_CTRL_SPLIT_LOCK_DETECT);
Updating the cache is at best unnecessary, and at worst dangerous, e.g. it
incorrectly implies that the cached value of SPLIT_LOCK_DETECT is reliable.
Tony's patch[*] is more what I had in mind, the only question is whether the
kernel should be paranoid about other bits in MSR_TEST_CTL.
[*] 20200206004944.GA11455@agluck-desk2.amr.corp.intel.com
> - wrmsrl(MSR_TEST_CTRL, test_ctrl_val);
> + wrmsrl(MSR_TEST_CTRL, this_cpu_read(msr_test_ctrl_cache));
> }
>
> static void split_lock_init(void)
> {
> + u64 test_ctrl_val;
> +
> + /* Cache MSR TEST_CTRL */
> + rdmsrl(MSR_TEST_CTRL, test_ctrl_val);
> + this_cpu_write(msr_test_ctrl_cache, test_ctrl_val);
> +
> if (sld_state == sld_off)
> return;
>
> --
> 2.23.0
>
next prev parent reply other threads:[~2020-03-03 19:18 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-06 7:04 [PATCH v3 0/8] kvm/split_lock: Add feature split lock detection support in kvm Xiaoyao Li
2020-02-06 7:04 ` [PATCH v3 1/8] x86/split_lock: Export handle_user_split_lock() Xiaoyao Li
2020-03-03 18:42 ` Sean Christopherson
2020-02-06 7:04 ` [PATCH v3 2/8] x86/split_lock: Ensure X86_FEATURE_SPLIT_LOCK_DETECT means the existence of feature Xiaoyao Li
2020-03-03 18:55 ` Sean Christopherson
2020-03-03 19:41 ` Sean Christopherson
2020-03-04 1:49 ` Xiaoyao Li
2020-03-05 16:23 ` Sean Christopherson
2020-03-06 2:15 ` Xiaoyao Li
2020-03-04 2:20 ` Xiaoyao Li
2020-02-06 7:04 ` [PATCH v3 3/8] x86/split_lock: Cache the value of MSR_TEST_CTRL in percpu data Xiaoyao Li
2020-02-06 20:23 ` Arvind Sankar
2020-02-07 4:18 ` Xiaoyao Li
2020-03-03 19:18 ` Sean Christopherson [this message]
2020-03-05 6:48 ` Xiaoyao Li
2020-02-06 7:04 ` [PATCH v3 4/8] x86/split_lock: Add and export split_lock_detect_enabled() and split_lock_detect_fatal() Xiaoyao Li
2020-03-03 18:59 ` Sean Christopherson
2020-02-06 7:04 ` [PATCH v3 5/8] kvm: x86: Emulate split-lock access as a write Xiaoyao Li
2020-02-06 7:04 ` [PATCH v3 6/8] kvm: vmx: Extend VMX's #AC interceptor to handle split lock #AC happens in guest Xiaoyao Li
2020-03-03 19:08 ` Sean Christopherson
2020-02-06 7:04 ` [PATCH v3 7/8] kvm: x86: Emulate MSR IA32_CORE_CAPABILITIES Xiaoyao Li
2020-02-06 7:04 ` [PATCH v3 8/8] x86: vmx: virtualize split lock detection Xiaoyao Li
2020-02-07 18:27 ` Arvind Sankar
2020-02-08 4:51 ` Xiaoyao Li
2020-03-03 19:30 ` Sean Christopherson
2020-03-05 14:16 ` Xiaoyao Li
2020-03-05 16:49 ` Sean Christopherson
2020-03-06 0:29 ` Xiaoyao Li
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