From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0B3BC43331 for ; Tue, 24 Mar 2020 17:46:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6C49A2076E for ; Tue, 24 Mar 2020 17:46:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="B+Tibpu8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727647AbgCXRqx (ORCPT ); Tue, 24 Mar 2020 13:46:53 -0400 Received: from us-smtp-delivery-74.mimecast.com ([63.128.21.74]:42444 "EHLO us-smtp-delivery-74.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727223AbgCXRqx (ORCPT ); Tue, 24 Mar 2020 13:46:53 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1585072011; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=qMQnlXZ4+W9pSmuD0MbvBFQqkeBh+78tD6YjGzWSr54=; b=B+Tibpu8m94XT4btI06lJV9NKesmHHAMYVLBa9LZt6l6ffx36qYEHubagqwAje7In9zU7j UInlU2B1rDHxOjz30YTz84n2o+axgoP1WP1dqtvJxnsonXmTIVCtHESLTT2itURe8eZWoQ CWaIPOSsK24BQUvsRF4l6+frRwGDlvQ= Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-364-6VCnKJ4RMM2tEuamwXFIhw-1; Tue, 24 Mar 2020 13:46:50 -0400 X-MC-Unique: 6VCnKJ4RMM2tEuamwXFIhw-1 Received: by mail-wm1-f71.google.com with SMTP id m4so1458119wmi.5 for ; Tue, 24 Mar 2020 10:46:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=qMQnlXZ4+W9pSmuD0MbvBFQqkeBh+78tD6YjGzWSr54=; b=Q31cypiMMxZ4YwxT8/ioC//z6/ousImxRmD9OsycRBWTOKU2mSEgcacnAifGVaK0o/ CaVsdQIXDDH0tcnaV1+Q+WC2PrfOTCO2qvuve4RkFvDUFK/vVPUfrh0nsBEwD5Hm9fy2 QB0k753yB72SKP0HW9nSUOAmpyUvOJpwb+t4pfYHPUl/fxSRb2O50pnr0Pwl4xToDaLX f7Ktg8+1vP0//SjliELFBZjtXABylCSy/J90eqxat3UJZ7KIn2GyI8rfAv4cFivOrSN9 fDBD7dvZ+4r1ikn0D7eVnMobgVKLYqJ2FfkbbeYGhoTzAItW2z+qZprY8ddsXWZefo81 Kwjg== X-Gm-Message-State: ANhLgQ1bq6knArypmxXA+b7cja9R6928m2T9vDpmw52aCAdHBVxzrJR1 BwxlWnHID3NDIfIxtVD8f5xgpuI5omgeDl/LmcVFHI+5oRZCuK01H/BnJGgK+PxP3Xus9+S9HoI IzjVDvwEhsQNf X-Received: by 2002:adf:aacc:: with SMTP id i12mr40213265wrc.116.1585072008978; Tue, 24 Mar 2020 10:46:48 -0700 (PDT) X-Google-Smtp-Source: ADFU+vt7Xq3xDq/ft0QrdRN3VE6gjTejZgxJ8O8JjoFJuohskC0CJwAJfPNCx07C/LnQgOVsCWmX5g== X-Received: by 2002:adf:aacc:: with SMTP id i12mr40213155wrc.116.1585072007766; Tue, 24 Mar 2020 10:46:47 -0700 (PDT) Received: from xz-x1 ([2607:9880:19c0:32::2]) by smtp.gmail.com with ESMTPSA id k15sm7063230wrm.55.2020.03.24.10.46.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Mar 2020 10:46:47 -0700 (PDT) Date: Tue, 24 Mar 2020 13:46:42 -0400 From: Peter Xu To: Liu Yi L Cc: qemu-devel@nongnu.org, alex.williamson@redhat.com, eric.auger@redhat.com, pbonzini@redhat.com, mst@redhat.com, david@gibson.dropbear.id.au, kevin.tian@intel.com, jun.j.tian@intel.com, yi.y.sun@intel.com, kvm@vger.kernel.org, hao.wu@intel.com, jean-philippe@linaro.org, Jacob Pan , Yi Sun , Richard Henderson Subject: Re: [PATCH v1 14/22] intel_iommu: bind/unbind guest page table to host Message-ID: <20200324174642.GY127076@xz-x1> References: <1584880579-12178-1-git-send-email-yi.l.liu@intel.com> <1584880579-12178-15-git-send-email-yi.l.liu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1584880579-12178-15-git-send-email-yi.l.liu@intel.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Sun, Mar 22, 2020 at 05:36:11AM -0700, Liu Yi L wrote: > This patch captures the guest PASID table entry modifications and > propagates the changes to host to setup dual stage DMA translation. > The guest page table is configured as 1st level page table (GVA->GPA) > whose translation result would further go through host VT-d 2nd > level page table(GPA->HPA) under nested translation mode. This is the > key part of vSVA support, and also a key to support IOVA over 1st- > level page table for Intel VT-d in virtualization environment. > > Cc: Kevin Tian > Cc: Jacob Pan > Cc: Peter Xu > Cc: Yi Sun > Cc: Paolo Bonzini > Cc: Richard Henderson > Signed-off-by: Liu Yi L > --- > hw/i386/intel_iommu.c | 98 +++++++++++++++++++++++++++++++++++++++--- > hw/i386/intel_iommu_internal.h | 25 +++++++++++ > 2 files changed, 118 insertions(+), 5 deletions(-) > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index c985cae..0423c83 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -41,6 +41,7 @@ > #include "migration/vmstate.h" > #include "trace.h" > #include "qemu/jhash.h" > +#include > > /* context entry operations */ > #define VTD_CE_GET_RID2PASID(ce) \ > @@ -695,6 +696,16 @@ static inline uint16_t vtd_pe_get_domain_id(VTDPASIDEntry *pe) > return VTD_SM_PASID_ENTRY_DID((pe)->val[1]); > } > > +static inline uint32_t vtd_pe_get_fl_aw(VTDPASIDEntry *pe) > +{ > + return 48 + ((pe->val[2] >> 2) & VTD_SM_PASID_ENTRY_FLPM) * 9; > +} > + > +static inline dma_addr_t vtd_pe_get_flpt_base(VTDPASIDEntry *pe) > +{ > + return pe->val[2] & VTD_SM_PASID_ENTRY_FLPTPTR; > +} > + > static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire) > { > return pdire->val & 1; > @@ -1856,6 +1867,81 @@ static void vtd_context_global_invalidate(IntelIOMMUState *s) > vtd_iommu_replay_all(s); > } > > +/** > + * Caller should hold iommu_lock. > + */ > +static int vtd_bind_guest_pasid(IntelIOMMUState *s, VTDBus *vtd_bus, > + int devfn, int pasid, VTDPASIDEntry *pe, > + VTDPASIDOp op) > +{ > + VTDHostIOMMUContext *vtd_dev_icx; > + HostIOMMUContext *host_icx; > + DualIOMMUStage1BindData *bind_data; > + struct iommu_gpasid_bind_data *g_bind_data; > + int ret = -1; > + > + vtd_dev_icx = vtd_bus->dev_icx[devfn]; > + if (!vtd_dev_icx) { > + return -EINVAL; > + } > + > + host_icx = vtd_dev_icx->host_icx; > + if (!host_icx) { > + return -EINVAL; > + } > + > + if (!(host_icx->stage1_formats > + & IOMMU_PASID_FORMAT_INTEL_VTD)) { > + error_report_once("IOMMU Stage 1 format is not compatible!\n"); Shouldn't we fail with this? > + } > + > + bind_data = g_malloc0(sizeof(*bind_data)); > + bind_data->pasid = pasid; > + g_bind_data = &bind_data->bind_data.gpasid_bind; > + > + g_bind_data->flags = 0; > + g_bind_data->vtd.flags = 0; > + switch (op) { > + case VTD_PASID_BIND: > + case VTD_PASID_UPDATE: Is VTD_PASID_UPDATE used anywhere? But since it's called "UPDATE"... I really want to confirm with you that the bind() to the kernel will handle the UPDATE case, right? I mean, we need to unbind first if there is an existing pgtable pointer. If the answer is yes, then I think we're good, but we really need to comment it somewhere about the fact. > + g_bind_data->version = IOMMU_UAPI_VERSION; > + g_bind_data->format = IOMMU_PASID_FORMAT_INTEL_VTD; > + g_bind_data->gpgd = vtd_pe_get_flpt_base(pe); > + g_bind_data->addr_width = vtd_pe_get_fl_aw(pe); > + g_bind_data->hpasid = pasid; > + g_bind_data->gpasid = pasid; > + g_bind_data->flags |= IOMMU_SVA_GPASID_VAL; > + g_bind_data->vtd.flags = > + (VTD_SM_PASID_ENTRY_SRE_BIT(pe->val[2]) ? 1 : 0) > + | (VTD_SM_PASID_ENTRY_EAFE_BIT(pe->val[2]) ? 1 : 0) > + | (VTD_SM_PASID_ENTRY_PCD_BIT(pe->val[1]) ? 1 : 0) > + | (VTD_SM_PASID_ENTRY_PWT_BIT(pe->val[1]) ? 1 : 0) > + | (VTD_SM_PASID_ENTRY_EMTE_BIT(pe->val[1]) ? 1 : 0) > + | (VTD_SM_PASID_ENTRY_CD_BIT(pe->val[1]) ? 1 : 0); > + g_bind_data->vtd.pat = VTD_SM_PASID_ENTRY_PAT(pe->val[1]); > + g_bind_data->vtd.emt = VTD_SM_PASID_ENTRY_EMT(pe->val[1]); > + ret = host_iommu_ctx_bind_stage1_pgtbl(host_icx, bind_data); > + break; > + case VTD_PASID_UNBIND: > + g_bind_data->version = IOMMU_UAPI_VERSION; > + g_bind_data->format = IOMMU_PASID_FORMAT_INTEL_VTD; > + g_bind_data->gpgd = 0; > + g_bind_data->addr_width = 0; > + g_bind_data->hpasid = pasid; > + g_bind_data->gpasid = pasid; > + g_bind_data->flags |= IOMMU_SVA_GPASID_VAL; > + ret = host_iommu_ctx_unbind_stage1_pgtbl(host_icx, bind_data); > + break; > + default: > + error_report_once("Unknown VTDPASIDOp!!!\n"); > + break; > + } > + > + g_free(bind_data); > + > + return ret; > +} > + > /* Do a context-cache device-selective invalidation. > * @func_mask: FM field after shifting > */ > @@ -2481,10 +2567,10 @@ static inline void vtd_fill_in_pe_in_cache(IntelIOMMUState *s, > > pc_entry->pasid_entry = *pe; > pc_entry->pasid_cache_gen = s->pasid_cache_gen; > - /* > - * TODO: > - * - send pasid bind to host for passthru devices > - */ > + vtd_bind_guest_pasid(s, vtd_pasid_as->vtd_bus, > + vtd_pasid_as->devfn, > + vtd_pasid_as->pasid, > + pe, VTD_PASID_BIND); > } > > /** > @@ -2574,11 +2660,13 @@ static gboolean vtd_flush_pasid(gpointer key, gpointer value, > * - when pasid-base-iotlb(piotlb) infrastructure is ready, > * should invalidate QEMU piotlb togehter with this change. > */ > + > return false; > remove: > + vtd_bind_guest_pasid(s, vtd_bus, devfn, > + pasid, NULL, VTD_PASID_UNBIND); > /* > * TODO: > - * - send pasid bind to host for passthru devices > * - when pasid-base-iotlb(piotlb) infrastructure is ready, > * should invalidate QEMU piotlb togehter with this change. > */ > diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h > index 01fd95c..4451acf 100644 > --- a/hw/i386/intel_iommu_internal.h > +++ b/hw/i386/intel_iommu_internal.h > @@ -516,6 +516,20 @@ typedef struct VTDRootEntry VTDRootEntry; > #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw)) > #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL > > +enum VTD_DUAL_STAGE_UAPI { > + UAPI_BIND_GPASID, > + UAPI_NUM > +}; > +typedef enum VTD_DUAL_STAGE_UAPI VTD_DUAL_STAGE_UAPI; > + > +enum VTDPASIDOp { > + VTD_PASID_BIND, > + VTD_PASID_UNBIND, > + VTD_PASID_UPDATE, Same here (whether to drop?). > + VTD_OP_NUM > +}; > +typedef enum VTDPASIDOp VTDPASIDOp; > + > struct VTDPASIDCacheInfo { > #define VTD_PASID_CACHE_GLOBAL (1ULL << 0) > #define VTD_PASID_CACHE_DOMSI (1ULL << 1) > @@ -552,6 +566,17 @@ typedef struct VTDPASIDCacheInfo VTDPASIDCacheInfo; > #define VTD_SM_PASID_ENTRY_AW 7ULL /* Adjusted guest-address-width */ > #define VTD_SM_PASID_ENTRY_DID(val) ((val) & VTD_DOMAIN_ID_MASK) > > +#define VTD_SM_PASID_ENTRY_FLPM 3ULL > +#define VTD_SM_PASID_ENTRY_FLPTPTR (~0xfffULL) > +#define VTD_SM_PASID_ENTRY_SRE_BIT(val) (!!((val) & 1ULL)) > +#define VTD_SM_PASID_ENTRY_EAFE_BIT(val) (!!(((val) >> 7) & 1ULL)) > +#define VTD_SM_PASID_ENTRY_PCD_BIT(val) (!!(((val) >> 31) & 1ULL)) > +#define VTD_SM_PASID_ENTRY_PWT_BIT(val) (!!(((val) >> 30) & 1ULL)) > +#define VTD_SM_PASID_ENTRY_EMTE_BIT(val) (!!(((val) >> 26) & 1ULL)) > +#define VTD_SM_PASID_ENTRY_CD_BIT(val) (!!(((val) >> 25) & 1ULL)) > +#define VTD_SM_PASID_ENTRY_PAT(val) (((val) >> 32) & 0xFFFFFFFFULL) > +#define VTD_SM_PASID_ENTRY_EMT(val) (((val) >> 27) & 0x7ULL) > + > /* Second Level Page Translation Pointer*/ > #define VTD_SM_PASID_ENTRY_SLPTPTR (~0xfffULL) > > -- > 2.7.4 > -- Peter Xu