From: Vivek Goyal <vgoyal@redhat.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <sean.j.christopherson@intel.com>,
Andy Lutomirski <luto@amacapital.net>,
Peter Zijlstra <peterz@infradead.org>,
Andy Lutomirski <luto@kernel.org>,
LKML <linux-kernel@vger.kernel.org>, X86 ML <x86@kernel.org>,
kvm list <kvm@vger.kernel.org>, stable <stable@vger.kernel.org>
Subject: Re: [PATCH v2] x86/kvm: Disable KVM_ASYNC_PF_SEND_ALWAYS
Date: Wed, 8 Apr 2020 16:34:25 -0400 [thread overview]
Message-ID: <20200408203425.GD93547@redhat.com> (raw)
In-Reply-To: <87d08hc0vz.fsf@nanos.tec.linutronix.de>
On Wed, Apr 08, 2020 at 08:01:36PM +0200, Thomas Gleixner wrote:
> Paolo Bonzini <pbonzini@redhat.com> writes:
> > On 08/04/20 17:34, Sean Christopherson wrote:
> >> On Wed, Apr 08, 2020 at 10:23:58AM +0200, Paolo Bonzini wrote:
> >>> Page-not-present async page faults are almost a perfect match for the
> >>> hardware use of #VE (and it might even be possible to let the processor
> >>> deliver the exceptions).
> >>
> >> My "async" page fault knowledge is limited, but if the desired behavior is
> >> to reflect a fault into the guest for select EPT Violations, then yes,
> >> enabling EPT Violation #VEs in hardware is doable. The big gotcha is that
> >> KVM needs to set the suppress #VE bit for all EPTEs when allocating a new
> >> MMU page, otherwise not-present faults on zero-initialized EPTEs will get
> >> reflected.
> >>
> >> Attached a patch that does the prep work in the MMU. The VMX usage would be:
> >>
> >> kvm_mmu_set_spte_init_value(VMX_EPT_SUPPRESS_VE_BIT);
> >>
> >> when EPT Violation #VEs are enabled. It's 64-bit only as it uses stosq to
> >> initialize EPTEs. 32-bit could also be supported by doing memcpy() from
> >> a static page.
> >
> > The complication is that (at least according to the current ABI) we
> > would not want #VE to kick if the guest currently has IF=0 (and possibly
> > CPL=0). But the ABI is not set in stone, and anyway the #VE protocol is
> > a decent one and worth using as a base for whatever PV protocol we design.
>
> Forget the current pf async semantics (or the lack of). You really want
> to start from scratch and igore the whole thing.
>
> The charm of #VE is that the hardware can inject it and it's not nesting
> until the guest cleared the second word in the VE information area. If
> that word is not 0 then you get a regular vmexit where you suspend the
> vcpu until the nested problem is solved.
So IIUC, only one process on a vcpu could affort to relinquish cpu to
another task. If next task also triggers EPT violation, that will result
in VM exit (as previous #VE is not complete yet) and vcpu will be halted.
>
> So you really don't worry about the guest CPU state at all. The guest
> side #VE handler has to decide what it wants from the host depending on
> it's internal state:
>
> - Suspend me and resume once the EPT fail is solved
>
> - Let me park the failing task and tell me once you resolved the
> problem.
>
> That's pretty straight forward and avoids the whole nonsense which the
> current mess contains. It completely avoids the allocation stuff as well
> as you need to use a PV page where the guest copies the VE information
> to.
>
> The notification that a problem has been resolved needs to go through a
> separate vector which still has the IF=1 requirement obviously.
How is this vector decided between guest and host. Failure to fault in
page will be communicated through same vector?
Thanks
Vivek
next prev parent reply other threads:[~2020-04-08 20:34 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-07 2:26 [PATCH v2] x86/kvm: Disable KVM_ASYNC_PF_SEND_ALWAYS Andy Lutomirski
2020-03-07 15:03 ` Andy Lutomirski
2020-03-07 15:47 ` Thomas Gleixner
2020-03-07 15:59 ` Andy Lutomirski
2020-03-07 19:01 ` Thomas Gleixner
2020-03-07 19:34 ` Andy Lutomirski
2020-03-08 7:23 ` Thomas Gleixner
2020-03-09 6:57 ` Thomas Gleixner
2020-03-09 8:40 ` Paolo Bonzini
2020-03-09 9:09 ` Thomas Gleixner
2020-03-09 18:14 ` Andy Lutomirski
2020-03-09 19:05 ` Thomas Gleixner
2020-03-09 20:22 ` Peter Zijlstra
2020-04-06 19:09 ` Vivek Goyal
2020-04-06 20:25 ` Peter Zijlstra
2020-04-06 20:32 ` Andy Lutomirski
2020-04-06 20:42 ` Andy Lutomirski
2020-04-07 17:21 ` Vivek Goyal
2020-04-07 17:38 ` Andy Lutomirski
2020-04-07 20:20 ` Thomas Gleixner
2020-04-07 21:41 ` Andy Lutomirski
2020-04-07 22:07 ` Paolo Bonzini
2020-04-07 22:29 ` Andy Lutomirski
2020-04-08 0:30 ` Paolo Bonzini
2020-05-21 15:55 ` Vivek Goyal
2020-04-07 22:48 ` Thomas Gleixner
2020-04-08 4:48 ` Andy Lutomirski
2020-04-08 9:32 ` Borislav Petkov
2020-04-08 10:12 ` Thomas Gleixner
2020-04-08 18:23 ` Vivek Goyal
2020-04-07 22:49 ` Vivek Goyal
2020-04-08 10:01 ` Borislav Petkov
2020-04-07 22:04 ` Paolo Bonzini
2020-04-07 23:21 ` Thomas Gleixner
2020-04-08 8:23 ` Paolo Bonzini
2020-04-08 13:01 ` Thomas Gleixner
2020-04-08 15:38 ` Peter Zijlstra
2020-04-08 16:41 ` Thomas Gleixner
2020-04-09 9:03 ` Paolo Bonzini
2020-04-08 15:34 ` Sean Christopherson
2020-04-08 16:50 ` Paolo Bonzini
2020-04-08 18:01 ` Thomas Gleixner
2020-04-08 20:34 ` Vivek Goyal [this message]
2020-04-08 23:06 ` Thomas Gleixner
2020-04-08 23:14 ` Thomas Gleixner
2020-04-09 4:50 ` Andy Lutomirski
2020-04-09 9:43 ` Paolo Bonzini
2020-04-09 11:36 ` Andrew Cooper
2020-04-09 12:47 ` Paolo Bonzini
2020-04-09 14:13 ` Andrew Cooper
2020-04-09 14:32 ` Paolo Bonzini
2020-04-09 15:03 ` Andy Lutomirski
2020-04-09 15:17 ` Paolo Bonzini
2020-04-09 17:32 ` Andy Lutomirski
2020-04-06 21:32 ` Thomas Gleixner
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