From: Sean Christopherson <sean.j.christopherson@intel.com>
To: Peter Xu <peterx@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Subject: Re: [PATCH 8/9] KVM: x86, SVM: do not clobber guest DR6 on KVM_EXIT_DEBUG
Date: Wed, 6 May 2020 14:20:47 -0700 [thread overview]
Message-ID: <20200506212047.GI3329@linux.intel.com> (raw)
In-Reply-To: <20200506211356.GD228260@xz-x1>
On Wed, May 06, 2020 at 05:13:56PM -0400, Peter Xu wrote:
> Oh... so is dr6 going to have some leftover bit set in the GD test if without
> this patch for AMD? Btw, I noticed a small difference on Intel/AMD spec for
> this case, e.g., B[0-3] definitions on such leftover bits...
>
> Intel says:
>
> B0 through B3 (breakpoint condition detected) flags (bits 0 through 3)
> — Indicates (when set) that its associated breakpoint condition was met
> when a debug exception was generated. These flags are set if the
> condition described for each breakpoint by the LENn, and R/Wn flags in
> debug control register DR7 is true. They may or may not be set if the
> breakpoint is not enabled by the Ln or the Gn flags in register
> DR7. Therefore on a #DB, a debug handler should check only those B0-B3
> bits which correspond to an enabled breakpoint.
>
> AMD says:
>
> Breakpoint-Condition Detected (B3–B0)—Bits 3:0. The processor updates
> these four bits on every debug breakpoint or general-detect
> condition. A bit is set to 1 if the corresponding address- breakpoint
> register detects an enabled breakpoint condition, as specified by the
> DR7 Ln, Gn, R/Wn and LENn controls, and is cleared to 0 otherwise. For
> example, B1 (bit 1) is set to 1 if an address- breakpoint condition is
> detected by DR1.
>
> I'm not sure whether it means AMD B[0-3] bits are more strict on the Intel ones
> (if so, then the selftest could be a bit too strict to VMX).
If the question is "can DR6 bits 3:0 be set on Intel CPUs even if the
associated breakpoint is disabled?", then the answer is yes. I haven't
looked at the selftest, but if it's checking DR6 then it should ignore
bits corresponding to disabled breakpoints.
next prev parent reply other threads:[~2020-05-06 21:20 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-06 11:10 [PATCH 0/9] KVM_SET_GUEST_DEBUG tests and fixes, DR accessors cleanups Paolo Bonzini
2020-05-06 11:10 ` [PATCH 1/9] KVM: X86: Declare KVM_CAP_SET_GUEST_DEBUG properly Paolo Bonzini
2020-05-06 11:10 ` [PATCH 2/9] KVM: x86: fix DR6 delivery for various cases of #DB injection Paolo Bonzini
2020-05-06 16:01 ` Peter Xu
2020-05-06 11:10 ` [PATCH 3/9] KVM: X86: Set RTM for DB_VECTOR too for KVM_EXIT_DEBUG Paolo Bonzini
2020-05-06 11:10 ` [PATCH 4/9] KVM: X86: Fix single-step with KVM_SET_GUEST_DEBUG Paolo Bonzini
2020-05-06 11:10 ` [PATCH 5/9] KVM: selftests: Add KVM_SET_GUEST_DEBUG test Paolo Bonzini
2020-05-06 11:10 ` [PATCH 6/9] KVM: SVM: keep DR6 synchronized with vcpu->arch.dr6 Paolo Bonzini
2020-05-06 16:04 ` Peter Xu
2020-05-06 11:10 ` [PATCH 7/9] KVM: x86: simplify dr6 accessors in kvm_x86_ops Paolo Bonzini
2020-05-06 16:06 ` Peter Xu
2020-05-06 16:09 ` Paolo Bonzini
2020-05-06 17:52 ` Peter Xu
2020-05-06 11:10 ` [PATCH 8/9] KVM: x86, SVM: do not clobber guest DR6 on KVM_EXIT_DEBUG Paolo Bonzini
2020-05-06 18:15 ` Peter Xu
2020-05-06 20:07 ` Paolo Bonzini
2020-05-06 21:13 ` Peter Xu
2020-05-06 21:20 ` Sean Christopherson [this message]
2020-05-06 23:33 ` Peter Xu
2020-05-06 23:47 ` Sean Christopherson
2020-05-06 11:10 ` [PATCH 9/9] KVM: VMX: pass correct DR6 for GD userspace exit Paolo Bonzini
2020-05-06 17:50 ` Peter Xu
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