From: Like Xu <like.xu@linux.intel.com>
To: kvm@vger.kernel.org, Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <sean.j.christopherson@intel.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>
Cc: Vitaly Kuznetsov <vkuznets@redhat.com>,
Joerg Roedel <joro@8bytes.org>,
wei.w.wang@intel.com, linux-kernel@vger.kernel.org,
Like Xu <like.xu@linux.intel.com>,
Kan Liang <kan.liang@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>
Subject: [PATCH 2/6] perf/x86/lbr: Unify LBR_INFO registers exposure check condition
Date: Fri, 31 Jul 2020 15:43:58 +0800 [thread overview]
Message-ID: <20200731074402.8879-3-like.xu@linux.intel.com> (raw)
In-Reply-To: <20200731074402.8879-1-like.xu@linux.intel.com>
Architectural LBR has IA32_LBR_x_INFO instead of LBR_FORMAT_INFO_x
to hold metadata for the operation, including mispredict, TSX, and
elapsed cycle time information.
The x86_pmu.lbr_info will be assigned in intel_pmu_?_lbr_init_?(),
it's safe to expose LBR_INFO in the x86_perf_get_lbr(), instead of
relying solely on 'lbr_format == LBR_FORMAT_INFO' check.
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
---
arch/x86/events/intel/lbr.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index 63f58bdf556c..8d816f580342 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -1832,12 +1832,10 @@ void __init intel_pmu_arch_lbr_init(void)
*/
int x86_perf_get_lbr(struct x86_pmu_lbr *lbr)
{
- int lbr_fmt = x86_pmu.intel_cap.lbr_format;
-
lbr->nr = x86_pmu.lbr_nr;
lbr->from = x86_pmu.lbr_from;
lbr->to = x86_pmu.lbr_to;
- lbr->info = (lbr_fmt == LBR_FORMAT_INFO) ? x86_pmu.lbr_info : 0;
+ lbr->info = x86_pmu.lbr_info;
return 0;
}
--
2.21.3
next prev parent reply other threads:[~2020-07-31 7:46 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-31 7:43 [PATCH 0/6] Guest Architectural LBR Enabling Like Xu
2020-07-31 7:43 ` [PATCH 1/6] KVM: vmx/pmu: Add VMCS field check before exposing LBR_FMT Like Xu
2020-07-31 7:43 ` Like Xu [this message]
2020-07-31 7:43 ` [PATCH 3/6] KVM: vmx/pmu: Add MSR_ARCH_LBR_DEPTH emulation for Arch LBR Like Xu
2020-07-31 7:44 ` [PATCH 4/6] KVM: vmx/pmu: Add MSR_ARCH_LBR_CTL " Like Xu
2020-07-31 7:44 ` [PATCH 5/6] KVM: vmx/pmu: Add Arch LBR emulation and its VMCS field Like Xu
2020-07-31 7:44 ` [PATCH 6/6] KVM: x86: Expose Architectural LBR CPUID and its XSAVES bit Like Xu
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