From: Yifei Jiang <jiangyifei@huawei.com>
To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>
Cc: <kvm-riscv@lists.infradead.org>, <kvm@vger.kernel.org>,
<libvir-list@redhat.com>, <anup.patel@wdc.com>,
<palmer@dabbelt.com>, <Alistair.Francis@wdc.com>,
<sagark@eecs.berkeley.edu>, <kbastian@mail.uni-paderborn.de>,
<victor.zhangxiaofeng@huawei.com>, <wu.wubin@huawei.com>,
<zhang.zhanghailiang@huawei.com>, <dengkai1@huawei.com>,
<yinyipeng1@huawei.com>, Yifei Jiang <jiangyifei@huawei.com>
Subject: [PATCH RFC v4 07/15] hw/riscv: PLIC update external interrupt by KVM when kvm enabled
Date: Thu, 3 Dec 2020 20:46:55 +0800 [thread overview]
Message-ID: <20201203124703.168-8-jiangyifei@huawei.com> (raw)
In-Reply-To: <20201203124703.168-1-jiangyifei@huawei.com>
Only support supervisor external interrupt currently.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
hw/intc/sifive_plic.c | 31 ++++++++++++++++++++++---------
target/riscv/kvm.c | 19 +++++++++++++++++++
target/riscv/kvm_riscv.h | 1 +
3 files changed, 42 insertions(+), 9 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 97a1a27a9a..a419ca3a3c 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -31,6 +31,8 @@
#include "target/riscv/cpu.h"
#include "sysemu/sysemu.h"
#include "migration/vmstate.h"
+#include "sysemu/kvm.h"
+#include "kvm_riscv.h"
#define RISCV_DEBUG_PLIC 0
@@ -147,15 +149,26 @@ static void sifive_plic_update(SiFivePLICState *plic)
continue;
}
int level = sifive_plic_irqs_pending(plic, addrid);
- switch (mode) {
- case PLICMode_M:
- riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
- break;
- case PLICMode_S:
- riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level));
- break;
- default:
- break;
+ if (kvm_enabled()) {
+ if (mode == PLICMode_M) {
+ continue;
+ }
+#ifdef CONFIG_KVM
+ kvm_riscv_set_irq(RISCV_CPU(cpu), IRQ_S_EXT, level);
+#endif
+ } else {
+ switch (mode) {
+ case PLICMode_M:
+ riscv_cpu_update_mip(RISCV_CPU(cpu),
+ MIP_MEIP, BOOL_TO_MASK(level));
+ break;
+ case PLICMode_S:
+ riscv_cpu_update_mip(RISCV_CPU(cpu),
+ MIP_SEIP, BOOL_TO_MASK(level));
+ break;
+ default:
+ break;
+ }
}
}
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 6250ca0c7d..b01ff0754c 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -454,3 +454,22 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
env->satp = 0;
}
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
+{
+ int ret;
+ unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET;
+
+ if (irq != IRQ_S_EXT) {
+ return;
+ }
+
+ if (!kvm_enabled()) {
+ return;
+ }
+
+ ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
+ if (ret < 0) {
+ perror("Set irq failed");
+ abort();
+ }
+}
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index f38c82bf59..ed281bdce0 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -20,5 +20,6 @@
#define QEMU_KVM_RISCV_H
void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
#endif
--
2.19.1
next prev parent reply other threads:[~2020-12-03 12:48 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-03 12:46 [PATCH RFC v4 00/15] Add riscv kvm accel support Yifei Jiang
2020-12-03 12:46 ` [PATCH RFC v4 01/15] linux-header: Update linux/kvm.h Yifei Jiang
2020-12-03 12:46 ` [PATCH RFC v4 02/15] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang
2020-12-03 12:46 ` [PATCH RFC v4 03/15] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang
2020-12-08 22:13 ` Alistair Francis
2020-12-03 12:46 ` [PATCH RFC v4 04/15] target/riscv: Implement kvm_arch_get_registers Yifei Jiang
2020-12-03 12:46 ` [PATCH RFC v4 05/15] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
2020-12-03 12:46 ` [PATCH RFC v4 06/15] target/riscv: Support start kernel directly by KVM Yifei Jiang
2020-12-08 22:19 ` Alistair Francis
2020-12-15 7:19 ` Jiangyifei
2020-12-03 12:46 ` Yifei Jiang [this message]
2020-12-08 22:29 ` [PATCH RFC v4 07/15] hw/riscv: PLIC update external interrupt by KVM when kvm enabled Alistair Francis
2020-12-15 7:33 ` Jiangyifei
2020-12-03 12:46 ` [PATCH RFC v4 08/15] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang
2020-12-03 12:46 ` [PATCH RFC v4 09/15] target/riscv: Add host cpu type Yifei Jiang
2020-12-08 22:21 ` Alistair Francis
2020-12-15 7:21 ` Jiangyifei
2020-12-03 12:46 ` [PATCH RFC v4 10/15] target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang
2020-12-03 12:46 ` [PATCH RFC v4 11/15] target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang
2020-12-03 12:47 ` [PATCH RFC v4 12/15] target/riscv: Support virtual time context synchronization Yifei Jiang
2020-12-03 12:47 ` [PATCH RFC v4 13/15] target/riscv: Introduce dynamic time frequency for virt machine Yifei Jiang
2020-12-08 22:25 ` Alistair Francis
2020-12-15 7:31 ` Jiangyifei
2021-01-05 17:36 ` Alistair Francis
2020-12-03 12:47 ` [PATCH RFC v4 14/15] target/riscv: Synchronize vcpu's frequency with KVM Yifei Jiang
2020-12-03 12:47 ` [PATCH RFC v4 15/15] target/riscv: Add time frequency migration support Yifei Jiang
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