From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Laurent Vivier" <laurent@vivier.eu>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Huacai Chen" <chenhuacai@kernel.org>,
kvm@vger.kernel.org
Subject: [PATCH 6/7] target/mips: Declare generic FPU functions in 'fpu_translate.h'
Date: Tue, 8 Dec 2020 00:55:38 +0100 [thread overview]
Message-ID: <20201207235539.4070364-7-f4bug@amsat.org> (raw)
In-Reply-To: <20201207235539.4070364-1-f4bug@amsat.org>
Some FPU translation functions / registers can be used by
ISA / ASE / extensions out of the big translate.c file.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/fpu_translate.h | 25 +++++++++++++++++++++++++
target/mips/translate.c | 14 ++++++++------
2 files changed, 33 insertions(+), 6 deletions(-)
create mode 100644 target/mips/fpu_translate.h
diff --git a/target/mips/fpu_translate.h b/target/mips/fpu_translate.h
new file mode 100644
index 00000000000..430e0b77537
--- /dev/null
+++ b/target/mips/fpu_translate.h
@@ -0,0 +1,25 @@
+/*
+ * FPU-related MIPS translation routines.
+ *
+ * Copyright (C) 2004-2005 Jocelyn Mayer
+ * Copyright (c) 2006 Marius Groeger (FPU operations)
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#ifndef TARGET_MIPS_FPU_TRANSLATE_H
+#define TARGET_MIPS_FPU_TRANSLATE_H
+
+#include "exec/translator.h"
+#include "translate.h"
+
+extern TCGv_i32 fpu_fcr0, fpu_fcr31;
+extern TCGv_i64 fpu_f64[32];
+
+void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
+void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
+
+int get_fp_bit(int cc);
+
+void check_cp1_enabled(DisasContext *ctx);
+
+#endif
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6614512a828..bc54eb58c70 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -40,7 +40,9 @@
#include "exec/log.h"
#include "qemu/qemu-print.h"
#include "fpu_helper.h"
+
#include "translate.h"
+#include "fpu_translate.h"
enum {
/* indirect opcode tables */
@@ -2496,8 +2498,8 @@ static TCGv cpu_dspctrl, btarget;
TCGv bcond;
static TCGv cpu_lladdr, cpu_llval;
static TCGv_i32 hflags;
-static TCGv_i32 fpu_fcr0, fpu_fcr31;
-static TCGv_i64 fpu_f64[32];
+TCGv_i32 fpu_fcr0, fpu_fcr31;
+TCGv_i64 fpu_f64[32];
static TCGv_i64 msa_wr_d[64];
#if defined(TARGET_MIPS64)
@@ -2813,7 +2815,7 @@ static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg)
}
}
-static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
+void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
{
if (ctx->hflags & MIPS_HFLAG_F64) {
tcg_gen_mov_i64(t, fpu_f64[reg]);
@@ -2822,7 +2824,7 @@ static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
}
}
-static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
+void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
{
if (ctx->hflags & MIPS_HFLAG_F64) {
tcg_gen_mov_i64(fpu_f64[reg], t);
@@ -2836,7 +2838,7 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
}
}
-static inline int get_fp_bit(int cc)
+int get_fp_bit(int cc)
{
if (cc) {
return 24 + cc;
@@ -2911,7 +2913,7 @@ static inline void check_cp0_enabled(DisasContext *ctx)
}
}
-static inline void check_cp1_enabled(DisasContext *ctx)
+void check_cp1_enabled(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) {
generate_exception_err(ctx, EXCP_CpU, 1);
--
2.26.2
next prev parent reply other threads:[~2020-12-07 23:57 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-07 23:55 [PATCH 0/7] target/mips: Add translate.h and fpu_translate.h headers Philippe Mathieu-Daudé
2020-12-07 23:55 ` [PATCH 1/7] target/mips/translate: Extract DisasContext structure Philippe Mathieu-Daudé
2020-12-08 22:53 ` Richard Henderson
2020-12-07 23:55 ` [PATCH 2/7] target/mips/translate: Add declarations for generic code Philippe Mathieu-Daudé
2020-12-08 22:53 ` Richard Henderson
2020-12-07 23:55 ` [PATCH 3/7] target/mips: Use FloatRoundMode enum for FCR31 modes conversion Philippe Mathieu-Daudé
2020-12-07 23:55 ` [PATCH 4/7] target/mips: Extract FPU helpers to 'fpu_helper.h' Philippe Mathieu-Daudé
2020-12-07 23:55 ` [PATCH 5/7] target/mips/fpu_helper: Remove unused headers Philippe Mathieu-Daudé
2020-12-08 22:53 ` Richard Henderson
2020-12-07 23:55 ` Philippe Mathieu-Daudé [this message]
2020-12-08 22:54 ` [PATCH 6/7] target/mips: Declare generic FPU functions in 'fpu_translate.h' Richard Henderson
2020-12-14 14:41 ` Philippe Mathieu-Daudé
2020-12-07 23:55 ` [PATCH 7/7] target/mips: Extract FPU specific definitions to fpu_translate.h Philippe Mathieu-Daudé
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