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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id w8sm10003601wrl.91.2021.01.07.14.27.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:27:39 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 55/66] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes Date: Thu, 7 Jan 2021 23:22:42 +0100 Message-Id: <20210107222253.20382-56-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add the LSA opcode to the MSA32 decodetree config, add DLSA to a new config for the MSA64 ASE, and call decode_msa64() in the main decode_opc() loop. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201215225757.764263-23-f4bug@amsat.org> --- target/mips/msa32.decode | 4 ++++ target/mips/msa64.decode | 17 +++++++++++++++++ target/mips/msa_translate.c | 14 ++++++++++++++ target/mips/meson.build | 1 + 4 files changed, 36 insertions(+) create mode 100644 target/mips/msa64.decode diff --git a/target/mips/msa32.decode b/target/mips/msa32.decode index d69675132b8..0b2f0863251 100644 --- a/target/mips/msa32.decode +++ b/target/mips/msa32.decode @@ -10,11 +10,15 @@ # (Document Number: MD00866-2B-MSA32-AFP-01.12) # +&lsa rd rt rs sa &msa_bz df wt s16 +@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa @bz ...... ... .. wt:5 s16:16 &msa_bz df=3 @bz_df ...... ... df:2 wt:5 s16:16 &msa_bz +LSA 000000 ..... ..... ..... 000 .. 000101 @lsa + BZ_V 010001 01011 ..... ................ @bz BNZ_V 010001 01111 ..... ................ @bz diff --git a/target/mips/msa64.decode b/target/mips/msa64.decode new file mode 100644 index 00000000000..8dcbbcd8538 --- /dev/null +++ b/target/mips/msa64.decode @@ -0,0 +1,17 @@ +# MIPS SIMD Architecture Module instruction set +# +# Copyright (C) 2020 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: +# MIPS Architecture for Programmers Volume IV-j +# The MIPS64 SIMD Architecture Module, Revision 1.12 +# (Document Number: MD00868-1D-MSA64-AFP-01.12) +# + +&lsa rd rt rs sa !extern + +@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa + +DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa diff --git a/target/mips/msa_translate.c b/target/mips/msa_translate.c index 8a48f889aa2..e97370e54c2 100644 --- a/target/mips/msa_translate.c +++ b/target/mips/msa_translate.c @@ -19,6 +19,7 @@ /* Include the auto-generated decoder. */ #include "decode-msa32.c.inc" +#include "decode-msa64.c.inc" #define OPC_MSA (0x1E << 26) @@ -2266,7 +2267,20 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) return true; } +static bool trans_LSA(DisasContext *ctx, arg_LSA *a) +{ + return gen_LSA(ctx, a->rd, a->rt, a->rs, a->sa); +} + +static bool trans_DLSA(DisasContext *ctx, arg_LSA *a) +{ + return gen_DLSA(ctx, a->rd, a->rt, a->rs, a->sa); +} + bool decode_ase_msa(DisasContext *ctx, uint32_t insn) { + if (TARGET_LONG_BITS == 64 && decode_msa64(ctx, insn)) { + return true; + } return decode_msa32(ctx, insn); } diff --git a/target/mips/meson.build b/target/mips/meson.build index 9afee0ca955..21b75254047 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -1,5 +1,6 @@ gen = [ decodetree.process('msa32.decode', extra_args: [ '--static-decode=decode_msa32' ]), + decodetree.process('msa64.decode', extra_args: [ '--static-decode=decode_msa64' ]), ] mips_ss = ss.source_set() -- 2.26.2