From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org
Cc: James Morse <james.morse@arm.com>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Eric Auger <eric.auger@redhat.com>,
kernel-team@android.com
Subject: [PATCH 3/6] KVM: arm64: Add handling of AArch32 PCMEID{2,3} PMUv3 registers
Date: Thu, 14 Jan 2021 10:56:30 +0000 [thread overview]
Message-ID: <20210114105633.2558739-4-maz@kernel.org> (raw)
In-Reply-To: <20210114105633.2558739-1-maz@kernel.org>
Despite advertising support for AArch32 PMUv3p1, we fail to handle
the PMCEID{2,3} registers, which conveniently alias with with the top
bits of PMCEID{0,1}_EL1.
Implement these registers with the usual AA32(HI/LO) aliasing
mechanism.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kvm/sys_regs.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index ce08d28ab15c..2bea0494b81d 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -685,14 +685,18 @@ static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
const struct sys_reg_desc *r)
{
- u64 pmceid;
+ u64 pmceid, mask, shift;
BUG_ON(p->is_write);
if (pmu_access_el0_disabled(vcpu))
return false;
+ get_access_mask(r, &mask, &shift);
+
pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1));
+ pmceid &= mask;
+ pmceid >>= shift;
p->regval = pmceid;
@@ -1895,8 +1899,8 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
{ Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
- { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
- { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
+ { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
+ { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
{ Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
{ Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
{ Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
@@ -1904,6 +1908,8 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
{ Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
{ Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
+ { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 4), access_pmceid },
+ { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 5), access_pmceid },
/* PRRR/MAIR0 */
{ AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
--
2.29.2
next prev parent reply other threads:[~2021-01-14 10:57 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-14 10:56 [PATCH 0/6] KVM: arm64: More PMU/debug ID register fixes Marc Zyngier
2021-01-14 10:56 ` [PATCH 1/6] KVM: arm64: Fix missing RES1 in emulation of DBGBIDR Marc Zyngier
2021-01-15 13:05 ` Auger Eric
2021-01-14 10:56 ` [PATCH 2/6] KVM: arm64: Fix AArch32 PMUv3 capping Marc Zyngier
2021-01-15 13:05 ` Auger Eric
2021-01-14 10:56 ` Marc Zyngier [this message]
2021-01-15 13:04 ` [PATCH 3/6] KVM: arm64: Add handling of AArch32 PCMEID{2,3} PMUv3 registers Auger Eric
2021-01-14 10:56 ` [PATCH 4/6] KVM: arm64: Refactor filtering of ID registers Marc Zyngier
2021-01-15 13:31 ` Auger Eric
2021-01-14 10:56 ` [PATCH 5/6] KVM: arm64: Limit the debug architecture to ARMv8.0 Marc Zyngier
2021-01-15 14:01 ` Auger Eric
2021-01-14 10:56 ` [PATCH 6/6] KVM: arm64: Upgrade PMU support to ARMv8.4 Marc Zyngier
2021-01-15 14:01 ` Auger Eric
2021-01-15 16:42 ` Marc Zyngier
2021-01-15 17:26 ` Auger Eric
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