From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF1EEC4332B for ; Fri, 15 Jan 2021 12:22:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8923F223E0 for ; Fri, 15 Jan 2021 12:22:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731680AbhAOMVw (ORCPT ); Fri, 15 Jan 2021 07:21:52 -0500 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:48523 "EHLO esa6.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731652AbhAOMVs (ORCPT ); Fri, 15 Jan 2021 07:21:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1610713306; x=1642249306; h=from:to:cc:subject:date:message-id:in-reply-to: references:content-transfer-encoding:mime-version; bh=fTyaWd/81z4y5vjB0aNAr+BvQeZI4/NmfzWNKQMEy8g=; b=ObkJEZb1KvSgut2TP3dfwhHui75kLjtqEaJw0URJbyKtrpRNZ1sBRvsX 24QyhxSqmw5Z8XyyUs772v74dIcqJDzkye/LQn0zVwW4rLclC5yLHDrgW TafSBCaDZF5m85D5kIfQrNenWN4Smu7V+eDOTPYvoN3EF1+Eqz7KoOYCM 5eFxsHEj2c3ZMgJ1QafeH3yQYyd1SeFrJ3zrBBX6Q7dR6XK8oJegFo+Sb QeZciFgrJI6TuukGN6a4PT2J8c7aONc/z4xT49u0rEQOTDhjCUTImSXSE IggqXRc3QfQWgJtdyBU2E8C0DqytmDmHF4/RA7hgSGx27ok5Fdrg81/1J g==; IronPort-SDR: wBhXnaIZ/PRkUWd4FXfk1A1DbEvwOnHZMydiWcrezYZBsDAvW1Be52/9CRax5iQmceOipcug4G s8hwvaI4OvK93AQKdCoK3eW+KRzPah3O7jck/BXEeBAPCzB5Qb2kJ66TmsvfWoJpdswyfiW7f9 fj3kuNNZHxXLO1gbkFxMX/li5pE7ecMK4OwrJ5AeVJ0ToAZlwsaSg89pqy9SHuarS0eU40sQQX 7AvNFd2GTebdXKkRKN93TSEd59jU0tcOY36Qsf/iDBHaKx3y1VRbs3yxtCYboLXExdqF51xIZk h4M= X-IronPort-AV: E=Sophos;i="5.79,349,1602518400"; d="scan'208";a="158687405" Received: from mail-bl2nam02lp2059.outbound.protection.outlook.com (HELO NAM02-BL2-obe.outbound.protection.outlook.com) ([104.47.38.59]) by ob1.hgst.iphmx.com with ESMTP; 15 Jan 2021 20:20:02 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=UiGr7ATan7wGWAnbAs/Y0B6P0QzInnwq93lVA4OrWB3PiiL/1hqyVHdTACsT2MPcy5sup/i53DN75rj8+9eXV5YytLwUtbg19FordTFyTdtVL2MDhyzAH8eVpESiWu+hVjl3kGm7IlAyspyH/U95ojIdMGW8k07auS533YOrT08BOSMVp2WfI1P/r0x/d/BiMQLWdz1vzjOwCKeEENUxhJFlZAt7n2b6DFsixNYg19q+tMN+y72h+guySWetO2PoYL+kcsXbFGzXTy+fY8iJ4MxDKTpkllCmeGAx5Av6ycm8Pc2X/WGE4zZViOdzK8leI2yYa5NojxjWH51WEM/YIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=M4Qj0UtRwrSQ5ohLZzVOkmYsEljNd39yxA4ELM9UXnU=; b=WD3Xtqdjy9zYB3+2bUfmmPyliPPWNoSuv9wRfRqJJ/WlQ3SdJKUPsd5GU5myHTKc/VLrFZplMBth6BW/WxPD/yVPAYTvjtPqPXmbpO7mORFZYp7lJ4MUwJs5MOvbfO9V6rdEWr8VLdWzVw7C9fJMlNGRwZfC79lDdv1X+tHypvIaxksykHvTcVbeS+i4RlFW1/uMjMSujDR1nDxdDz7AJdkTWya2bialZzyvlummklM5Bl5bOk+6FMUxdSZIEebxtqq2HcRcM14YaxdXL65VOU5uzCT+p2rSaLzBqejv3JC2UEKzVGg6kx/bmN1R71s4Tjjg43EQj90rG9LUqg0TLg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=M4Qj0UtRwrSQ5ohLZzVOkmYsEljNd39yxA4ELM9UXnU=; b=yGz8/4zy5fIL08PAZT6qfrSEkvQrK8Otmsmj1Cnfv26E/nROwXRRRpJOLc/X5AyIPGqruhhW35SKnHUd3EBQ8sUY2PvtDGIEK+f1xlPWWzY29DZXZYyqr8Ix5oRJjRJ2BXJB8DtnuGyPIw+XC1RXlRoqyQp+dV5xsjlYT9uuHMM= Authentication-Results: dabbelt.com; dkim=none (message not signed) header.d=none;dabbelt.com; dmarc=none action=none header.from=wdc.com; Received: from DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) by DM5PR04MB3769.namprd04.prod.outlook.com (2603:10b6:3:fc::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3763.10; Fri, 15 Jan 2021 12:20:01 +0000 Received: from DM6PR04MB6201.namprd04.prod.outlook.com ([fe80::2513:b200:bdc8:b97]) by DM6PR04MB6201.namprd04.prod.outlook.com ([fe80::2513:b200:bdc8:b97%5]) with mapi id 15.20.3742.012; Fri, 15 Jan 2021 12:20:01 +0000 From: Anup Patel To: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Albert Ou , Paolo Bonzini Cc: Alexander Graf , Atish Patra , Alistair Francis , Damien Le Moal , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v16 09/17] RISC-V: KVM: Implement VMID allocator Date: Fri, 15 Jan 2021 17:48:38 +0530 Message-Id: <20210115121846.114528-10-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115121846.114528-1-anup.patel@wdc.com> References: <20210115121846.114528-1-anup.patel@wdc.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [122.167.152.18] X-ClientProxiedBy: MAXPR0101CA0024.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:c::34) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (122.167.152.18) by MAXPR0101CA0024.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:c::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3763.10 via Frontend Transport; Fri, 15 Jan 2021 12:19:57 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 2a3ca252-445a-42ef-7f12-08d8b94fe1ba X-MS-TrafficTypeDiagnostic: DM5PR04MB3769: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SXpmuDhAImFaFxhDwGWaymvzZ6dQtay1+8CUTJfN9M38dfzRtjR3ClMne5r1jan13sd3zAoBJQ4Qe4Fi3Ny0YnGCCA0UnBsmEblZsEpphuQ6kvx72ZtZe9IDZ4Os74/rIjQtM7ihjD9wy6BLlzIXoOsIuwgXIWvlDaneYzF2o089nq/njwyQ872dkmMr0V8Ha6Io28foLXu4F/pmsnfe/G9LkFj9+QvgOL4vSUAaPwD/ZDYQMDB+NNYESxzb1dQ+4aB14+UoHPhS6HOVElCNsTh1cpZ3DMI8cHJ2GCixj9hANPx3/K+mYUIRhag013p/JjnRv00w7mTDC2McsFKKAkIS+a02zcNT8m4oyTpErpOOXnyjzcGuwdCVDHs2qJMYX7a+rBPzqkILX+IlTChtEQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM6PR04MB6201.namprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(39860400002)(346002)(136003)(366004)(376002)(396003)(66476007)(6666004)(55016002)(7696005)(54906003)(66946007)(110136005)(956004)(5660300002)(2616005)(186003)(52116002)(44832011)(478600001)(66556008)(8936002)(26005)(86362001)(2906002)(83380400001)(7416002)(30864003)(16526019)(8676002)(316002)(4326008)(36756003)(8886007)(1076003);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?EF62Gj8uu9/w87UFAjMbWTeLHaLxXMXpKrTKrEcrJiEym9RYhrDMoHsWHIpC?= =?us-ascii?Q?NsU4EaPlllXc9QFZrJuNlINkNp90aZLfdQUwaSULSJDa9oNoiV3EQvch1RpA?= =?us-ascii?Q?xy0jThEidKdgjuY7RvBuy3jl868PalYbOd6688AobEvyTdCQCzK3pBxIQ6Ve?= =?us-ascii?Q?z+aLMtRyNAely23uDqjKlqGe8N3RUrNFrU6FrD3bJb5r8losgDqagCU6onxG?= =?us-ascii?Q?dw3z0t5IsJae85+ZsbGrH3XazZd2yV12Rz1/SoZJRe8/pzxaVIx1rJ/f59+w?= =?us-ascii?Q?P0+RO6aWjjgDv3y6aoRaT4IeJv7gPAIq3GG1spUUpjTtmKHtLXtcgjTAwE+l?= =?us-ascii?Q?K+EmbpNHGCEmrFgei7jKY/WBF0q25FbOW56ZknbaygAzoFzmvi4874U8BOAg?= =?us-ascii?Q?tKi42RbH037aMmdVCkHwqroDHdcf8zeFY+D35TACFKYkrIwU9e7QsoPsz8qI?= =?us-ascii?Q?of6a10f+2sBGl2ucROuNQPuXFsbjlLQ6nYD3g7B5D6CD7ipg42K2i3HqrhbA?= =?us-ascii?Q?yYnqLUhpGKHzRWQ2pRiOS6iE0oj3Qs9lpqI7pWjP7L5Qf8R5AFOiH/3I8GSg?= =?us-ascii?Q?hgDJ1eRbtNLjAnnDhwUym5yOVinXavJ827ESbQ5A5Xwna2fTDv7C3LPJQtCB?= =?us-ascii?Q?fyES6kEM8qTPmnNNt5OsGqdC3O2R3VAXd+myArFsQ14TUptk12Kbzzvbozbo?= =?us-ascii?Q?xPKBSacXvwA3yNtAbQA67etBfmbEpGi0AM2CbFz/k4yE678g/jNUx/or6UPN?= =?us-ascii?Q?iFOaSLkEXjScu+Dv5sUAYbXws6gJIgWurSyT9SFbPltRbJJTJgoDTy/2tEvd?= =?us-ascii?Q?a3hlETD3/iuvrGXvCIqEkht/By4QkZEpLCKTGjqhIc8MYztUp4AlqhNjTEtL?= =?us-ascii?Q?tf2RmBTSu+kiYT+MJ2sxurhAecT2kdZs8nYAMGI4oe1rRM0fbNlwgLWm5uS5?= =?us-ascii?Q?PVyOeO3QPjiYFiZTGSXKjZJRm5lt0B2KrJ0n07IU7YjmvAnq5KKsDe+th1YS?= =?us-ascii?Q?N2VC?= X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2a3ca252-445a-42ef-7f12-08d8b94fe1ba X-MS-Exchange-CrossTenant-AuthSource: DM6PR04MB6201.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jan 2021 12:20:01.5954 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: QkVDS03dQ7+rGBNOK2gyGNkcXTWjv+SoRVPOOSaM1adLKZDx/eJIS3FKhI1ZwAS4dz38nqN8nzJ3oGI+U7a1/A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR04MB3769 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org We implement a simple VMID allocator for Guests/VMs which: 1. Detects number of VMID bits at boot-time 2. Uses atomic number to track VMID version and increments VMID version whenever we run-out of VMIDs 3. Flushes Guest TLBs on all host CPUs whenever we run-out of VMIDs 4. Force updates HW Stage2 VMID for each Guest VCPU whenever VMID changes using VCPU request KVM_REQ_UPDATE_HGATP Signed-off-by: Anup Patel Acked-by: Paolo Bonzini Reviewed-by: Paolo Bonzini Reviewed-by: Alexander Graf --- arch/riscv/include/asm/kvm_host.h | 24 ++++++ arch/riscv/kvm/Makefile | 3 +- arch/riscv/kvm/main.c | 4 + arch/riscv/kvm/tlb.S | 74 ++++++++++++++++++ arch/riscv/kvm/vcpu.c | 9 +++ arch/riscv/kvm/vm.c | 6 ++ arch/riscv/kvm/vmid.c | 120 ++++++++++++++++++++++++++++++ 7 files changed, 239 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/kvm/tlb.S create mode 100644 arch/riscv/kvm/vmid.c diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index bfc9fca6b049..ca4eb4ce1335 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -27,6 +27,7 @@ #define KVM_REQ_SLEEP \ KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(1) +#define KVM_REQ_UPDATE_HGATP KVM_ARCH_REQ(2) struct kvm_vm_stat { ulong remote_tlb_flush; @@ -49,7 +50,19 @@ struct kvm_vcpu_stat { struct kvm_arch_memory_slot { }; +struct kvm_vmid { + /* + * Writes to vmid_version and vmid happen with vmid_lock held + * whereas reads happen without any lock held. + */ + unsigned long vmid_version; + unsigned long vmid; +}; + struct kvm_arch { + /* stage2 vmid */ + struct kvm_vmid vmid; + /* stage2 page table */ pgd_t *pgd; phys_addr_t pgd_phys; @@ -180,6 +193,11 @@ static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {} static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} +void __kvm_riscv_hfence_gvma_vmid_gpa(unsigned long gpa, unsigned long vmid); +void __kvm_riscv_hfence_gvma_vmid(unsigned long vmid); +void __kvm_riscv_hfence_gvma_gpa(unsigned long gpa); +void __kvm_riscv_hfence_gvma_all(void); + int kvm_riscv_stage2_map(struct kvm_vcpu *vcpu, struct kvm_memory_slot *memslot, gpa_t gpa, unsigned long hva, bool is_write); @@ -188,6 +206,12 @@ int kvm_riscv_stage2_alloc_pgd(struct kvm *kvm); void kvm_riscv_stage2_free_pgd(struct kvm *kvm); void kvm_riscv_stage2_update_hgatp(struct kvm_vcpu *vcpu); +void kvm_riscv_stage2_vmid_detect(void); +unsigned long kvm_riscv_stage2_vmid_bits(void); +int kvm_riscv_stage2_vmid_init(struct kvm *kvm); +bool kvm_riscv_stage2_vmid_ver_changed(struct kvm_vmid *vmid); +void kvm_riscv_stage2_vmid_update(struct kvm_vcpu *vcpu); + void __kvm_riscv_unpriv_trap(void); unsigned long kvm_riscv_vcpu_unpriv_read(struct kvm_vcpu *vcpu, diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index 54991cc55c00..b32f60edf48c 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -9,6 +9,7 @@ ccflags-y := -Ivirt/kvm -Iarch/riscv/kvm kvm-objs := $(common-objs-y) -kvm-objs += main.o vm.o mmu.o vcpu.o vcpu_exit.o vcpu_switch.o +kvm-objs += main.o vm.o vmid.o tlb.o mmu.o +kvm-objs += vcpu.o vcpu_exit.o vcpu_switch.o obj-$(CONFIG_KVM) += kvm.o diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c index 47926f0c175d..49a4941e3838 100644 --- a/arch/riscv/kvm/main.c +++ b/arch/riscv/kvm/main.c @@ -79,8 +79,12 @@ int kvm_arch_init(void *opaque) return -ENODEV; } + kvm_riscv_stage2_vmid_detect(); + kvm_info("hypervisor extension available\n"); + kvm_info("VMID %ld bits available\n", kvm_riscv_stage2_vmid_bits()); + return 0; } diff --git a/arch/riscv/kvm/tlb.S b/arch/riscv/kvm/tlb.S new file mode 100644 index 000000000000..c858570f0856 --- /dev/null +++ b/arch/riscv/kvm/tlb.S @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#include +#include + + .text + .altmacro + .option norelax + + /* + * Instruction encoding of hfence.gvma is: + * HFENCE.GVMA rs1, rs2 + * HFENCE.GVMA zero, rs2 + * HFENCE.GVMA rs1 + * HFENCE.GVMA + * + * rs1!=zero and rs2!=zero ==> HFENCE.GVMA rs1, rs2 + * rs1==zero and rs2!=zero ==> HFENCE.GVMA zero, rs2 + * rs1!=zero and rs2==zero ==> HFENCE.GVMA rs1 + * rs1==zero and rs2==zero ==> HFENCE.GVMA + * + * Instruction encoding of HFENCE.GVMA is: + * 0110001 rs2(5) rs1(5) 000 00000 1110011 + */ + +ENTRY(__kvm_riscv_hfence_gvma_vmid_gpa) + /* + * rs1 = a0 (GPA) + * rs2 = a1 (VMID) + * HFENCE.GVMA a0, a1 + * 0110001 01011 01010 000 00000 1110011 + */ + .word 0x62b50073 + ret +ENDPROC(__kvm_riscv_hfence_gvma_vmid_gpa) + +ENTRY(__kvm_riscv_hfence_gvma_vmid) + /* + * rs1 = zero + * rs2 = a0 (VMID) + * HFENCE.GVMA zero, a0 + * 0110001 01010 00000 000 00000 1110011 + */ + .word 0x62a00073 + ret +ENDPROC(__kvm_riscv_hfence_gvma_vmid) + +ENTRY(__kvm_riscv_hfence_gvma_gpa) + /* + * rs1 = a0 (GPA) + * rs2 = zero + * HFENCE.GVMA a0 + * 0110001 00000 01010 000 00000 1110011 + */ + .word 0x62050073 + ret +ENDPROC(__kvm_riscv_hfence_gvma_gpa) + +ENTRY(__kvm_riscv_hfence_gvma_all) + /* + * rs1 = zero + * rs2 = zero + * HFENCE.GVMA + * 0110001 00000 00000 000 00000 1110011 + */ + .word 0x62000073 + ret +ENDPROC(__kvm_riscv_hfence_gvma_all) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 43962a25fa55..7192b6edd826 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -637,6 +637,12 @@ static void kvm_riscv_check_vcpu_requests(struct kvm_vcpu *vcpu) if (kvm_check_request(KVM_REQ_VCPU_RESET, vcpu)) kvm_riscv_reset_vcpu(vcpu); + + if (kvm_check_request(KVM_REQ_UPDATE_HGATP, vcpu)) + kvm_riscv_stage2_update_hgatp(vcpu); + + if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) + __kvm_riscv_hfence_gvma_all(); } } @@ -682,6 +688,8 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) /* Check conditions before entering the guest */ cond_resched(); + kvm_riscv_stage2_vmid_update(vcpu); + kvm_riscv_check_vcpu_requests(vcpu); preempt_disable(); @@ -718,6 +726,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) kvm_riscv_update_hvip(vcpu); if (ret <= 0 || + kvm_riscv_stage2_vmid_ver_changed(&vcpu->kvm->arch.vmid) || kvm_request_pending(vcpu)) { vcpu->mode = OUTSIDE_GUEST_MODE; local_irq_enable(); diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c index 496a86a74236..282d67617229 100644 --- a/arch/riscv/kvm/vm.c +++ b/arch/riscv/kvm/vm.c @@ -26,6 +26,12 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) if (r) return r; + r = kvm_riscv_stage2_vmid_init(kvm); + if (r) { + kvm_riscv_stage2_free_pgd(kvm); + return r; + } + return 0; } diff --git a/arch/riscv/kvm/vmid.c b/arch/riscv/kvm/vmid.c new file mode 100644 index 000000000000..2c6253b293bc --- /dev/null +++ b/arch/riscv/kvm/vmid.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static unsigned long vmid_version = 1; +static unsigned long vmid_next; +static unsigned long vmid_bits; +static DEFINE_SPINLOCK(vmid_lock); + +void kvm_riscv_stage2_vmid_detect(void) +{ + unsigned long old; + + /* Figure-out number of VMID bits in HW */ + old = csr_read(CSR_HGATP); + csr_write(CSR_HGATP, old | HGATP_VMID_MASK); + vmid_bits = csr_read(CSR_HGATP); + vmid_bits = (vmid_bits & HGATP_VMID_MASK) >> HGATP_VMID_SHIFT; + vmid_bits = fls_long(vmid_bits); + csr_write(CSR_HGATP, old); + + /* We polluted local TLB so flush all guest TLB */ + __kvm_riscv_hfence_gvma_all(); + + /* We don't use VMID bits if they are not sufficient */ + if ((1UL << vmid_bits) < num_possible_cpus()) + vmid_bits = 0; +} + +unsigned long kvm_riscv_stage2_vmid_bits(void) +{ + return vmid_bits; +} + +int kvm_riscv_stage2_vmid_init(struct kvm *kvm) +{ + /* Mark the initial VMID and VMID version invalid */ + kvm->arch.vmid.vmid_version = 0; + kvm->arch.vmid.vmid = 0; + + return 0; +} + +bool kvm_riscv_stage2_vmid_ver_changed(struct kvm_vmid *vmid) +{ + if (!vmid_bits) + return false; + + return unlikely(READ_ONCE(vmid->vmid_version) != + READ_ONCE(vmid_version)); +} + +void kvm_riscv_stage2_vmid_update(struct kvm_vcpu *vcpu) +{ + int i; + struct kvm_vcpu *v; + struct cpumask hmask; + struct kvm_vmid *vmid = &vcpu->kvm->arch.vmid; + + if (!kvm_riscv_stage2_vmid_ver_changed(vmid)) + return; + + spin_lock(&vmid_lock); + + /* + * We need to re-check the vmid_version here to ensure that if + * another vcpu already allocated a valid vmid for this vm. + */ + if (!kvm_riscv_stage2_vmid_ver_changed(vmid)) { + spin_unlock(&vmid_lock); + return; + } + + /* First user of a new VMID version? */ + if (unlikely(vmid_next == 0)) { + WRITE_ONCE(vmid_version, READ_ONCE(vmid_version) + 1); + vmid_next = 1; + + /* + * We ran out of VMIDs so we increment vmid_version and + * start assigning VMIDs from 1. + * + * This also means existing VMIDs assignement to all Guest + * instances is invalid and we have force VMID re-assignement + * for all Guest instances. The Guest instances that were not + * running will automatically pick-up new VMIDs because will + * call kvm_riscv_stage2_vmid_update() whenever they enter + * in-kernel run loop. For Guest instances that are already + * running, we force VM exits on all host CPUs using IPI and + * flush all Guest TLBs. + */ + riscv_cpuid_to_hartid_mask(cpu_online_mask, &hmask); + sbi_remote_hfence_gvma(cpumask_bits(&hmask), 0, 0); + } + + vmid->vmid = vmid_next; + vmid_next++; + vmid_next &= (1 << vmid_bits) - 1; + + WRITE_ONCE(vmid->vmid_version, READ_ONCE(vmid_version)); + + spin_unlock(&vmid_lock); + + /* Request stage2 page table update for all VCPUs */ + kvm_for_each_vcpu(i, v, vcpu->kvm) + kvm_make_request(KVM_REQ_UPDATE_HGATP, v); +} -- 2.25.1