From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org
Cc: James Morse <james.morse@arm.com>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Eric Auger <eric.auger@redhat.com>,
kernel-team@android.com
Subject: [PATCH v2 4/7] KVM: arm64: Refactor filtering of ID registers
Date: Mon, 25 Jan 2021 12:26:35 +0000 [thread overview]
Message-ID: <20210125122638.2947058-5-maz@kernel.org> (raw)
In-Reply-To: <20210125122638.2947058-1-maz@kernel.org>
Our current ID register filtering is starting to be a mess of if()
statements, and isn't going to get any saner.
Let's turn it into a switch(), which has a chance of being more
readable, and introduce a FEATURE() macro that allows easy generation
of feature masks.
No functionnal change intended.
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kvm/sys_regs.c | 51 +++++++++++++++++++++------------------
1 file changed, 28 insertions(+), 23 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 2bea0494b81d..dda16d60197b 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -9,6 +9,7 @@
* Christoffer Dall <c.dall@virtualopensystems.com>
*/
+#include <linux/bitfield.h>
#include <linux/bsearch.h>
#include <linux/kvm_host.h>
#include <linux/mm.h>
@@ -1016,6 +1017,8 @@ static bool access_arch_timer(struct kvm_vcpu *vcpu,
return true;
}
+#define FEATURE(x) (GENMASK_ULL(x##_SHIFT + 3, x##_SHIFT))
+
/* Read a sanitised cpufeature ID register by sys_reg_desc */
static u64 read_id_reg(const struct kvm_vcpu *vcpu,
struct sys_reg_desc const *r, bool raz)
@@ -1024,36 +1027,38 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
(u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
u64 val = raz ? 0 : read_sanitised_ftr_reg(id);
- if (id == SYS_ID_AA64PFR0_EL1) {
+ switch (id) {
+ case SYS_ID_AA64PFR0_EL1:
if (!vcpu_has_sve(vcpu))
- val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
- val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT);
- val &= ~(0xfUL << ID_AA64PFR0_CSV2_SHIFT);
- val |= ((u64)vcpu->kvm->arch.pfr0_csv2 << ID_AA64PFR0_CSV2_SHIFT);
- val &= ~(0xfUL << ID_AA64PFR0_CSV3_SHIFT);
- val |= ((u64)vcpu->kvm->arch.pfr0_csv3 << ID_AA64PFR0_CSV3_SHIFT);
- } else if (id == SYS_ID_AA64PFR1_EL1) {
- val &= ~(0xfUL << ID_AA64PFR1_MTE_SHIFT);
- } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) {
- val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) |
- (0xfUL << ID_AA64ISAR1_API_SHIFT) |
- (0xfUL << ID_AA64ISAR1_GPA_SHIFT) |
- (0xfUL << ID_AA64ISAR1_GPI_SHIFT));
- } else if (id == SYS_ID_AA64DFR0_EL1) {
- u64 cap = 0;
-
+ val &= ~FEATURE(ID_AA64PFR0_SVE);
+ val &= ~FEATURE(ID_AA64PFR0_AMU);
+ val &= ~FEATURE(ID_AA64PFR0_CSV2);
+ val |= FIELD_PREP(FEATURE(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2);
+ val &= ~FEATURE(ID_AA64PFR0_CSV3);
+ val |= FIELD_PREP(FEATURE(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3);
+ break;
+ case SYS_ID_AA64PFR1_EL1:
+ val &= ~FEATURE(ID_AA64PFR1_MTE);
+ break;
+ case SYS_ID_AA64ISAR1_EL1:
+ if (!vcpu_has_ptrauth(vcpu))
+ val &= ~(FEATURE(ID_AA64ISAR1_APA) |
+ FEATURE(ID_AA64ISAR1_API) |
+ FEATURE(ID_AA64ISAR1_GPA) |
+ FEATURE(ID_AA64ISAR1_GPI));
+ break;
+ case SYS_ID_AA64DFR0_EL1:
/* Limit guests to PMUv3 for ARMv8.1 */
- if (kvm_vcpu_has_pmu(vcpu))
- cap = ID_AA64DFR0_PMUVER_8_1;
-
val = cpuid_feature_cap_perfmon_field(val,
- ID_AA64DFR0_PMUVER_SHIFT,
- cap);
- } else if (id == SYS_ID_DFR0_EL1) {
+ ID_AA64DFR0_PMUVER_SHIFT,
+ kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_1 : 0);
+ break;
+ case SYS_ID_DFR0_EL1:
/* Limit guests to PMUv3 for ARMv8.1 */
val = cpuid_feature_cap_perfmon_field(val,
ID_DFR0_PERFMON_SHIFT,
kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_1 : 0);
+ break;
}
return val;
--
2.29.2
next prev parent reply other threads:[~2021-01-26 20:22 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-25 12:26 [PATCH v2 0/7] KVM: arm64: More PMU/debug ID register fixes Marc Zyngier
2021-01-25 12:26 ` [PATCH v2 1/7] KVM: arm64: Fix missing RES1 in emulation of DBGBIDR Marc Zyngier
2021-01-26 17:32 ` Alexandru Elisei
2021-01-25 12:26 ` [PATCH v2 2/7] KVM: arm64: Fix AArch32 PMUv3 capping Marc Zyngier
2021-01-26 17:35 ` Alexandru Elisei
2021-01-25 12:26 ` [PATCH v2 3/7] KVM: arm64: Add handling of AArch32 PCMEID{2,3} PMUv3 registers Marc Zyngier
2021-01-25 12:26 ` Marc Zyngier [this message]
2021-01-27 12:12 ` [PATCH v2 4/7] KVM: arm64: Refactor filtering of ID registers Alexandru Elisei
2021-01-25 12:26 ` [PATCH v2 5/7] KVM: arm64: Limit the debug architecture to ARMv8.0 Marc Zyngier
2021-01-27 12:18 ` Alexandru Elisei
2021-01-25 12:26 ` [PATCH v2 6/7] KVM: arm64: Upgrade PMU support to ARMv8.4 Marc Zyngier
2021-01-27 14:09 ` Alexandru Elisei
2021-01-27 14:35 ` Marc Zyngier
2021-01-27 17:00 ` Alexandru Elisei
2021-01-27 17:23 ` Marc Zyngier
2021-01-27 17:41 ` Alexandru Elisei
2021-02-03 10:32 ` Marc Zyngier
2021-02-03 17:29 ` Alexandru Elisei
2021-01-27 17:53 ` Auger Eric
2021-02-03 10:36 ` Marc Zyngier
2021-02-03 11:07 ` Auger Eric
2021-02-03 11:20 ` Marc Zyngier
2021-02-03 12:39 ` Auger Eric
2021-02-03 13:28 ` Marc Zyngier
2021-02-04 12:32 ` Alexandru Elisei
2021-02-04 14:21 ` Marc Zyngier
2021-01-25 12:26 ` [PATCH v2 7/7] KVM: arm64: Use symbolic names for the PMU versions Marc Zyngier
2021-01-27 14:28 ` Alexandru Elisei
2021-01-27 17:56 ` Auger Eric
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