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From: Yanan Wang <wangyanan55@huawei.com>
To: <kvmarm@lists.cs.columbia.edu>,
	<linux-arm-kernel@lists.infradead.org>, <kvm@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, Marc Zyngier <maz@kernel.org>,
	Will Deacon <will@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	James Morse <james.morse@arm.com>,
	Julien Thierry <julien.thierry.kdev@gmail.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	<wanghaibin.wang@huawei.com>, <yezengruan@huawei.com>,
	<zhukeqian1@huawei.com>, <yuzenghui@huawei.com>,
	Yanan Wang <wangyanan55@huawei.com>
Subject: [RFC PATCH v1 5/5] KVM: arm64: Adapt page-table code to new handling of coalescing tables
Date: Tue, 26 Jan 2021 21:42:02 +0800	[thread overview]
Message-ID: <20210126134202.381996-6-wangyanan55@huawei.com> (raw)
In-Reply-To: <20210126134202.381996-1-wangyanan55@huawei.com>

With new handling of coalescing tables, we can install the block entry
before unmap of the old table mappings. So make the installation in
stage2_map_walk_table_pre(), and elide the installation from function
stage2_map_walk_table_post().

Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
---
 arch/arm64/kvm/hyp/pgtable.c | 25 ++++++++++++-------------
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c
index ab1c94985ed0..fb755aac4384 100644
--- a/arch/arm64/kvm/hyp/pgtable.c
+++ b/arch/arm64/kvm/hyp/pgtable.c
@@ -436,6 +436,7 @@ struct stage2_map_data {
 	kvm_pte_t			attr;
 
 	kvm_pte_t			*anchor;
+	kvm_pte_t			*follow;
 
 	struct kvm_s2_mmu		*mmu;
 	struct kvm_mmu_memory_cache	*memcache;
@@ -550,13 +551,13 @@ static int stage2_map_walk_table_pre(u64 addr, u64 end, u32 level,
 	kvm_set_invalid_pte(ptep);
 
 	/*
-	 * Invalidate the whole stage-2, as we may have numerous leaf
-	 * entries below us which would otherwise need invalidating
-	 * individually.
+	 * If there is an existing table entry and block mapping is needed here,
+	 * then set the anchor and replace it with a block entry. The sub-level
+	 * mappings will later be unmapped lazily.
 	 */
-	kvm_call_hyp(__kvm_tlb_flush_vmid, data->mmu);
 	data->anchor = ptep;
-	return 0;
+	data->follow = kvm_pte_follow(*ptep);
+	return stage2_coalesce_tables_into_block(addr, level, ptep, data);
 }
 
 static int stage2_map_walk_leaf(u64 addr, u64 end, u32 level, kvm_pte_t *ptep,
@@ -608,20 +609,18 @@ static int stage2_map_walk_table_post(u64 addr, u64 end, u32 level,
 				      kvm_pte_t *ptep,
 				      struct stage2_map_data *data)
 {
-	int ret = 0;
-
 	if (!data->anchor)
 		return 0;
 
-	free_page((unsigned long)kvm_pte_follow(*ptep));
-	put_page(virt_to_page(ptep));
-
-	if (data->anchor == ptep) {
+	if (data->anchor != ptep) {
+		free_page((unsigned long)kvm_pte_follow(*ptep));
+		put_page(virt_to_page(ptep));
+	} else {
+		free_page((unsigned long)data->follow);
 		data->anchor = NULL;
-		ret = stage2_map_walk_leaf(addr, end, level, ptep, data);
 	}
 
-	return ret;
+	return 0;
 }
 
 /*
-- 
2.19.1


  parent reply	other threads:[~2021-01-26 13:50 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-26 13:41 [RFC PATCH v1 0/5] Enable CPU TTRem feature for stage-2 Yanan Wang
2021-01-26 13:41 ` [RFC PATCH v1 1/5] arm64: cpufeature: Detect the ARMv8.4 TTRem feature Yanan Wang
2021-01-26 13:41 ` [RFC PATCH v1 2/5] arm64: cpufeature: Add an API to get level of TTRem supported by hardware Yanan Wang
2021-01-26 13:42 ` [RFC PATCH v1 3/5] KVM: arm64: Support usage of TTRem in guest stage-2 translation Yanan Wang
2021-01-26 13:42 ` [RFC PATCH v1 4/5] KVM: arm64: Add handling of coalescing tables into a block mapping Yanan Wang
2021-01-26 13:42 ` Yanan Wang [this message]
2021-01-26 14:18 ` [RFC PATCH v1 0/5] Enable CPU TTRem feature for stage-2 Marc Zyngier

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