From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6702DC433E6 for ; Fri, 19 Feb 2021 12:14:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2077A64EB8 for ; Fri, 19 Feb 2021 12:14:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229524AbhBSMO3 (ORCPT ); Fri, 19 Feb 2021 07:14:29 -0500 Received: from foss.arm.com ([217.140.110.172]:35034 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229599AbhBSMOW (ORCPT ); Fri, 19 Feb 2021 07:14:22 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D600A12FC; Fri, 19 Feb 2021 04:13:36 -0800 (PST) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 047543F73B; Fri, 19 Feb 2021 04:13:35 -0800 (PST) From: Alexandru Elisei To: drjones@redhat.com, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Cc: andre.przywara@arm.com, eric.auger@redhat.com Subject: [kvm-unit-tests PATCH v4 03/11] arm/arm64: gic: Remove SMP synchronization from ipi_clear_active_handler() Date: Fri, 19 Feb 2021 12:13:29 +0000 Message-Id: <20210219121337.76533-4-alexandru.elisei@arm.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210219121337.76533-1-alexandru.elisei@arm.com> References: <20210219121337.76533-1-alexandru.elisei@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The gicv{2,3}-active test sends an IPI from the boot CPU to itself, then checks that the interrupt has been received as expected. There is no need to use inter-processor memory synchronization primitives on code that runs on the same CPU, so remove the unneeded memory barriers. Reviewed-by: Eric Auger Reviewed-by: Andre Przywara Signed-off-by: Alexandru Elisei --- arm/gic.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arm/gic.c b/arm/gic.c index e2e053aeb823..8bb804abf34d 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -367,6 +367,7 @@ static struct gic gicv3 = { }, }; +/* Runs on the same CPU as the sender, no need for memory synchronization */ static void ipi_clear_active_handler(struct pt_regs *regs __unused) { u32 irqstat = gic_read_iar(); @@ -383,13 +384,10 @@ static void ipi_clear_active_handler(struct pt_regs *regs __unused) writel(val, base + GICD_ICACTIVER); - smp_rmb(); /* pairs with wmb in stats_reset */ ++acked[smp_processor_id()]; check_irqnr(irqnr); - smp_wmb(); /* pairs with rmb in check_acked */ } else { ++spurious[smp_processor_id()]; - smp_wmb(); } } -- 2.30.1