From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D568C43333 for ; Thu, 4 Mar 2021 00:28:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5587564E62 for ; Thu, 4 Mar 2021 00:28:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1381657AbhCDA16 (ORCPT ); Wed, 3 Mar 2021 19:27:58 -0500 Received: from mga11.intel.com ([192.55.52.93]:44167 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237820AbhCCOHF (ORCPT ); Wed, 3 Mar 2021 09:07:05 -0500 IronPort-SDR: E6QrcAV/BdPf1uD+RY9MIu+8OnQ9ekhwSzaeVKLirk//2PQwNJODkYmTn3T2M93T8PEqff5aJ0 hii7wqzgmJ9Q== X-IronPort-AV: E=McAfee;i="6000,8403,9911"; a="183818863" X-IronPort-AV: E=Sophos;i="5.81,220,1610438400"; d="scan'208";a="183818863" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2021 06:05:21 -0800 IronPort-SDR: 6Wx2avFZ5NZp2xVnxL+aL91JvjJZFYXOZ39fhjwpVQcXzC8J82qZzKUM2jJE09cwXhEHrQNX5b rwoHWjarqz5w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,220,1610438400"; d="scan'208";a="399729328" Received: from clx-ap-likexu.sh.intel.com ([10.239.48.108]) by fmsmga008.fm.intel.com with ESMTP; 03 Mar 2021 06:05:14 -0800 From: Like Xu To: Peter Zijlstra , Paolo Bonzini , Sean Christopherson Cc: Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , Kan Liang , Dave Hansen , wei.w.wang@intel.com, Borislav Petkov , kvm@vger.kernel.org, x86@kernel.org, linux-kernel@vger.kernel.org, Like Xu Subject: [PATCH v3 2/9] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers Date: Wed, 3 Mar 2021 21:57:48 +0800 Message-Id: <20210303135756.1546253-3-like.xu@linux.intel.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210303135756.1546253-1-like.xu@linux.intel.com> References: <20210303135756.1546253-1-like.xu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org If the platform supports LBR_INFO register, the x86_pmu.lbr_info will be assigned in intel_pmu_?_lbr_init_?() and it's safe to expose LBR_INFO in the x86_perf_get_lbr() directly, instead of relying on lbr_format check. Also Architectural LBR has IA32_LBR_x_INFO instead of LBR_FORMAT_INFO_x to hold metadata for the operation, including mispredict, TSX, and elapsed cycle time information. Cc: Peter Zijlstra Reviewed-by: Kan Liang Signed-off-by: Like Xu --- arch/x86/events/intel/lbr.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index 21890dacfcfe..355ea70f1879 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -1832,12 +1832,10 @@ void __init intel_pmu_arch_lbr_init(void) */ int x86_perf_get_lbr(struct x86_pmu_lbr *lbr) { - int lbr_fmt = x86_pmu.intel_cap.lbr_format; - lbr->nr = x86_pmu.lbr_nr; lbr->from = x86_pmu.lbr_from; lbr->to = x86_pmu.lbr_to; - lbr->info = (lbr_fmt == LBR_FORMAT_INFO) ? x86_pmu.lbr_info : 0; + lbr->info = x86_pmu.lbr_info; return 0; } -- 2.29.2