From: Like Xu <like.xu@linux.intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>
Cc: Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
kvm@vger.kernel.org, x86@kernel.org, wei.w.wang@intel.com,
linux-kernel@vger.kernel.org, Like Xu <like.xu@linux.intel.com>,
Kan Liang <kan.liang@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Borislav Petkov <bp@alien8.de>, Ingo Molnar <mingo@redhat.com>
Subject: [PATCH v4 05/11] perf/x86: Move ARCH_LBR_CTL_MASK definition to include/asm/msr-index.h
Date: Sun, 14 Mar 2021 23:52:18 +0800 [thread overview]
Message-ID: <20210314155225.206661-6-like.xu@linux.intel.com> (raw)
In-Reply-To: <20210314155225.206661-1-like.xu@linux.intel.com>
The ARCH_LBR_CTL_MASK will be reused for LBR emulation in the KVM.
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Ingo Molnar <mingo@redhat.com>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
---
arch/x86/events/intel/lbr.c | 2 --
arch/x86/include/asm/msr-index.h | 1 +
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index 237876733e12..f60339ff0c13 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -168,8 +168,6 @@ enum {
ARCH_LBR_RETURN |\
ARCH_LBR_OTHER_BRANCH)
-#define ARCH_LBR_CTL_MASK 0x7f000e
-
static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc);
static __always_inline bool is_lbr_call_stack_bit_set(u64 config)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 546d6ecf0a35..8f3375961efc 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -169,6 +169,7 @@
#define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET)
#define MSR_ARCH_LBR_CTL 0x000014ce
+#define ARCH_LBR_CTL_MASK 0x7f000e
#define ARCH_LBR_CTL_LBREN BIT(0)
#define ARCH_LBR_CTL_CPL_OFFSET 1
#define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET)
--
2.29.2
next prev parent reply other threads:[~2021-03-14 16:01 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-14 15:52 [PATCH v4 00/11] KVM: x86/pmu: Guest Architectural LBR Enabling Like Xu
2021-03-14 15:52 ` [PATCH v4 01/11] perf/x86/intel: Fix the comment about guest LBR support on KVM Like Xu
2021-03-14 15:52 ` [PATCH v4 02/11] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers Like Xu
2021-03-14 15:52 ` [PATCH v4 03/11] perf/x86/lbr: Skip checking for the existence of LBR_TOS for Arch LBR Like Xu
2021-03-14 15:52 ` [PATCH v4 04/11] perf/x86/lbr: Move cpuc->lbr_xsave allocation out of sleeping region Like Xu
2021-03-14 15:52 ` Like Xu [this message]
2021-03-14 15:52 ` [PATCH v4 06/11] KVM: vmx/pmu: Add MSR_ARCH_LBR_DEPTH emulation for Arch LBR Like Xu
2021-03-14 15:52 ` [PATCH v4 07/11] KVM: vmx/pmu: Add MSR_ARCH_LBR_CTL " Like Xu
2021-03-14 15:52 ` [PATCH v4 08/11] KVM: vmx/pmu: Add Arch LBR emulation and its VMCS field Like Xu
2021-03-14 15:52 ` [PATCH v4 09/11] KVM: x86: Expose Architectural LBR CPUID leaf Like Xu
2021-03-14 15:52 ` [PATCH v4 10/11] KVM: x86: Refine the matching and clearing logic for supported_xss Like Xu
2021-03-14 15:52 ` [PATCH v4 11/11] KVM: x86: Add XSAVE Support for Architectural LBRs Like Xu
2021-03-14 15:52 ` [PATCH v2] x86: Update guest LBR tests for Architectural LBR Like Xu
2021-03-22 6:18 ` [PATCH v4 00/11] KVM: x86/pmu: Guest Architectural LBR Enabling Xu, Like
2021-04-06 3:19 ` Xu, Like
2021-04-21 2:25 ` Like Xu
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