From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9000BC43600 for ; Thu, 15 Apr 2021 03:21:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6A5AB611B0 for ; Thu, 15 Apr 2021 03:21:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229985AbhDODV2 (ORCPT ); Wed, 14 Apr 2021 23:21:28 -0400 Received: from mga01.intel.com ([192.55.52.88]:10590 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229926AbhDODV0 (ORCPT ); Wed, 14 Apr 2021 23:21:26 -0400 IronPort-SDR: wHEtk26TyRGWocB8+Kesrsg+wkStqg3DgbQzBqapEB/yMNswP2IOiy+m7QwYzhNvxqc+T0/Uuy dGFnO4rzMNjw== X-IronPort-AV: E=McAfee;i="6200,9189,9954"; a="215281570" X-IronPort-AV: E=Sophos;i="5.82,223,1613462400"; d="scan'208";a="215281570" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2021 20:21:04 -0700 IronPort-SDR: Cl5PE6NdmOH2Bkb6z8sjFBDOglX+3jU3qyXwhVTWmy/9w6yN32gUuIcKH9z/lsb9Tcoa2HZgos EAUkGMz4vhwQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,223,1613462400"; d="scan'208";a="425014052" Received: from clx-ap-likexu.sh.intel.com ([10.239.48.108]) by orsmga008.jf.intel.com with ESMTP; 14 Apr 2021 20:21:00 -0700 From: Like Xu To: peterz@infradead.org, Paolo Bonzini , Sean Christopherson Cc: andi@firstfloor.org, kan.liang@linux.intel.com, wei.w.wang@intel.com, eranian@google.com, liuxiangdong5@huawei.com, Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, x86@kernel.org, linux-kernel@vger.kernel.org, Like Xu Subject: [PATCH v5 10/16] KVM: x86: Set PEBS_UNAVAIL in IA32_MISC_ENABLE when PEBS is enabled Date: Thu, 15 Apr 2021 11:20:10 +0800 Message-Id: <20210415032016.166201-11-like.xu@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210415032016.166201-1-like.xu@linux.intel.com> References: <20210415032016.166201-1-like.xu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The bit 12 represents "Processor Event Based Sampling Unavailable (RO)" : 1 = PEBS is not supported. 0 = PEBS is supported. A write to this PEBS_UNAVL available bit will bring #GP(0) when guest PEBS is enabled. Some PEBS drivers in guest may care about this bit. Signed-off-by: Like Xu --- arch/x86/kvm/vmx/pmu_intel.c | 2 ++ arch/x86/kvm/x86.c | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 58f32a55cc2e..c846d3eef7a7 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -588,6 +588,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) bitmap_set(pmu->all_valid_pmc_idx, INTEL_PMC_IDX_FIXED_VLBR, 1); if (vcpu->arch.perf_capabilities & PERF_CAP_PEBS_FORMAT) { + vcpu->arch.ia32_misc_enable_msr &= ~MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL; if (vcpu->arch.perf_capabilities & PERF_CAP_PEBS_BASELINE) { pmu->pebs_enable_mask = ~pmu->global_ctrl; pmu->reserved_bits &= ~ICL_EVENTSEL_ADAPTIVE; @@ -597,6 +598,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) } pmu->pebs_data_cfg_mask = ~0xff00000full; } else { + vcpu->arch.ia32_misc_enable_msr |= MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL; pmu->pebs_enable_mask = ~((1ull << pmu->nr_arch_gp_counters) - 1); } diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 1a64e816e06d..ed38f1dada63 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -3126,6 +3126,10 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) break; case MSR_IA32_MISC_ENABLE: data &= ~MSR_IA32_MISC_ENABLE_EMON; + if (!msr_info->host_initiated && + (vcpu->arch.perf_capabilities & PERF_CAP_PEBS_FORMAT) && + (data & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL)) + return 1; if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) -- 2.30.2