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From: Yang Weijiang <weijiang.yang@intel.com>
To: pbonzini@redhat.com, seanjc@google.com, kvm@vger.kernel.org,
Cc: Yang Weijiang <weijiang.yang@intel.com>
Subject: [PATCH v6 2/3] KVM: nVMX: Set X86_CR4_CET in cr4_fixed1_bits if CET IBT is enabled
Date: Wed, 21 Apr 2021 17:05:51 +0800
Message-ID: <20210421090552.10403-3-weijiang.yang@intel.com> (raw)
In-Reply-To: <20210421090552.10403-1-weijiang.yang@intel.com>

CET SHSTK and IBT are independently controlled by kernel, set X86_CR4_CET
bit in cr4_fixed1_bits if either of them is enabled so that nested guest
can enjoy the feature.

Reviewed-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
 arch/x86/kvm/vmx/vmx.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index e78650bf8ae8..bd89b5a24c38 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -7267,6 +7267,7 @@ static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
 	cr4_fixed1_update(X86_CR4_UMIP,       ecx, feature_bit(UMIP));
 	cr4_fixed1_update(X86_CR4_LA57,       ecx, feature_bit(LA57));
 	cr4_fixed1_update(X86_CR4_CET,	      ecx, feature_bit(SHSTK));
+	cr4_fixed1_update(X86_CR4_CET,	      edx, feature_bit(IBT));
 #undef cr4_fixed1_update

  parent reply index

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-21  9:05 [PATCH v6 0/3] CET fix patches for nested guest Yang Weijiang
2021-04-21  9:05 ` [PATCH v6 1/3] KVM: nVMX: Sync L2 guest CET states between L1/L2 Yang Weijiang
2021-04-21  9:05 ` Yang Weijiang [this message]
2021-04-21  9:05 ` [PATCH v6 3/3] KVM: nVMX: Add CET entry/exit load bits to evmcs unsupported list Yang Weijiang

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