From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E002C12002 for ; Fri, 16 Jul 2021 07:14:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 42985613F0 for ; Fri, 16 Jul 2021 07:14:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236314AbhGPHRD (ORCPT ); Fri, 16 Jul 2021 03:17:03 -0400 Received: from mga02.intel.com ([134.134.136.20]:23864 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236333AbhGPHQy (ORCPT ); Fri, 16 Jul 2021 03:16:54 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10046"; a="197873286" X-IronPort-AV: E=Sophos;i="5.84,244,1620716400"; d="scan'208";a="197873286" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jul 2021 00:13:46 -0700 X-IronPort-AV: E=Sophos;i="5.84,244,1620716400"; d="scan'208";a="506375062" Received: from arthur-vostro-3668.sh.intel.com ([10.239.13.1]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jul 2021 00:13:41 -0700 From: Zeng Guang To: Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, Dave Hansen , Tony Luck , Kan Liang , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , Kim Phillips , Jarkko Sakkinen , Jethro Beekman , Kai Huang Cc: x86@kernel.org, linux-kernel@vger.kernel.org, Robert Hu , Gao Chao , Zeng Guang Subject: [PATCH 5/6] KVM: x86: Support interrupt dispatch in x2APIC mode with APIC-write VM exit Date: Fri, 16 Jul 2021 14:48:07 +0800 Message-Id: <20210716064808.14757-6-guang.zeng@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210716064808.14757-1-guang.zeng@intel.com> References: <20210716064808.14757-1-guang.zeng@intel.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Since IA x86 platform introduce features of IPI virtualization and User Interrupts, new behavior applies to the execution of WRMSR ICR register that causes APIC-write VM exit instead of MSR-write VM exit in x2APIC mode. This requires KVM to emulate writing 64-bit value to offset 300H on the virtual-APIC page(VICR) for guest running in x2APIC mode when APIC-wrtie VM exit occurs. Prevoisely KVM doesn't consider this situation as CPU never produce APIC-write VM exit in x2APIC mode before. Signed-off-by: Zeng Guang --- arch/x86/kvm/lapic.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index ba5a27879f1d..0b0f0ce96679 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2188,7 +2188,14 @@ void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset) /* hw has done the conditional check and inst decode */ offset &= 0xff0; - kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val); + if (apic_x2apic_mode(vcpu->arch.apic) && (offset == APIC_ICR)) { + u64 icr_val = *((u64 *)(vcpu->arch.apic->regs + offset)); + + kvm_lapic_reg_write(vcpu->arch.apic, APIC_ICR2, (u32)(icr_val>>32)); + val = (u32)icr_val; + } else { + kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val); + } /* TODO: optimize to just emulate side effect w/o one more write */ kvm_lapic_reg_write(vcpu->arch.apic, offset, val); -- 2.25.1