From: Wei Huang <wei.huang2@amd.com>
To: kvm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, pbonzini@redhat.com,
vkuznets@redhat.com, seanjc@google.com, wanpengli@tencent.com,
jmattson@google.com, joro@8bytes.org, tglx@linutronix.de,
mingo@redhat.com, bp@alien8.de, x86@kernel.org, hpa@zytor.com,
wei.huang2@amd.com
Subject: [PATCH v1 3/3] KVM: SVM: Add 5-level page table support for SVM
Date: Thu, 5 Aug 2021 15:55:04 -0500 [thread overview]
Message-ID: <20210805205504.2647362-4-wei.huang2@amd.com> (raw)
In-Reply-To: <20210805205504.2647362-1-wei.huang2@amd.com>
Future AMD CPUs will support 5-level page table which is indicated by
X86_CR4_LA57 flag. When the 5-level page table is enabled on host OS,
the nested page table for guest VMs must use 5-level as well. Update
get_npt_level() function to reflect this requirement. In the meanwhile,
remove the code that prevents kvm-amd driver from being loaded when
5-level page table is detected.
Signed-off-by: Wei Huang <wei.huang2@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
arch/x86/kvm/svm/svm.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 04710e10d04a..f91ff7d2d9f9 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -261,7 +261,9 @@ u32 svm_msrpm_offset(u32 msr)
static int svm_get_npt_level(struct kvm_vcpu *vcpu)
{
#ifdef CONFIG_X86_64
- return PT64_ROOT_4LEVEL;
+ bool la57 = (cr4_read_shadow() & X86_CR4_LA57) != 0;
+
+ return la57 ? PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
#else
return PT32E_ROOT_LEVEL;
#endif
@@ -462,11 +464,6 @@ static int has_svm(void)
return 0;
}
- if (pgtable_l5_enabled()) {
- pr_info("KVM doesn't yet support 5-level paging on AMD SVM\n");
- return 0;
- }
-
return 1;
}
--
2.31.1
prev parent reply other threads:[~2021-08-05 20:55 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-05 20:55 [PATCH v1 0/3] SVM 5-level page table support Wei Huang
2021-08-05 20:55 ` [PATCH v1 1/3] KVM: x86: Convert TDP level calculation to vendor's specific code Wei Huang
2021-08-05 21:51 ` Sean Christopherson
2021-08-05 22:26 ` Wei Huang
2021-08-08 19:30 ` Wei Huang
2021-08-05 22:35 ` Jim Mattson
2021-08-05 22:44 ` Sean Christopherson
2021-08-05 20:55 ` [PATCH v1 2/3] KVM: x86: Handle the case of 5-level shadow page table Wei Huang
2021-08-06 17:58 ` Sean Christopherson
2021-08-08 17:49 ` Wei Huang
2021-08-05 20:55 ` Wei Huang [this message]
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