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From: Zhu Lingshan <lingshan.zhu@intel.com>
To: peterz@infradead.org, pbonzini@redhat.com
Cc: bp@alien8.de, seanjc@google.com, vkuznets@redhat.com,
	wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org,
	kan.liang@linux.intel.com, ak@linux.intel.com,
	wei.w.wang@intel.com, eranian@google.com,
	liuxiangdong5@huawei.com, linux-kernel@vger.kernel.org,
	x86@kernel.org, kvm@vger.kernel.org, like.xu.linux@gmail.com,
	boris.ostrvsky@oracle.com, Like Xu <like.xu@linux.intel.com>,
	Zhu Lingshan <lingshan.zhu@intel.com>
Subject: [PATCH V10 10/18] KVM: x86/pmu: Adjust precise_ip to emulate Ice Lake guest PDIR counter
Date: Fri,  6 Aug 2021 21:37:54 +0800	[thread overview]
Message-ID: <20210806133802.3528-11-lingshan.zhu@intel.com> (raw)
In-Reply-To: <20210806133802.3528-1-lingshan.zhu@intel.com>

From: Like Xu <like.xu@linux.intel.com>

The PEBS-PDIR facility on Ice Lake server is supported on IA31_FIXED0 only.
If the guest configures counter 32 and PEBS is enabled, the PEBS-PDIR
facility is supposed to be used, in which case KVM adjusts attr.precise_ip
to 3 and request host perf to assign the exactly requested counter or fail.

The CPU model check is also required since some platforms may place the
PEBS-PDIR facility in another counter index.

Signed-off-by: Like Xu <like.xu@linux.intel.com>
Signed-off-by: Zhu Lingshan <lingshan.zhu@intel.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
 arch/x86/events/intel/core.c | 2 +-
 arch/x86/kvm/pmu.c           | 2 ++
 arch/x86/kvm/pmu.h           | 7 +++++++
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index d196b32617c5..b25c9d6be314 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3951,8 +3951,8 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
 
 	if (!x86_pmu.pebs_vmx)
 		return arr;
-	pebs_enable = (*nr)++;
 
+	pebs_enable = (*nr)++;
 	arr[pebs_enable] = (struct perf_guest_switch_msr){
 		.msr = MSR_IA32_PEBS_ENABLE,
 		.host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask,
diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
index d76b0a5d80d7..b907aba35ff3 100644
--- a/arch/x86/kvm/pmu.c
+++ b/arch/x86/kvm/pmu.c
@@ -153,6 +153,8 @@ static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
 		 * could possibly care here is unsupported and needs changes.
 		 */
 		attr.precise_ip = 1;
+		if (x86_match_cpu(vmx_icl_pebs_cpu) && pmc->idx == 32)
+			attr.precise_ip = 3;
 	}
 	if (pebs || intr)
 		ovf = kvm_perf_overflow_intr;
diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h
index 67e753edfa22..1af86ae1d3f2 100644
--- a/arch/x86/kvm/pmu.h
+++ b/arch/x86/kvm/pmu.h
@@ -4,6 +4,8 @@
 
 #include <linux/nospec.h>
 
+#include <asm/cpu_device_id.h>
+
 #define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu)
 #define pmu_to_vcpu(pmu)  (container_of((pmu), struct kvm_vcpu, arch.pmu))
 #define pmc_to_pmu(pmc)   (&(pmc)->vcpu->arch.pmu)
@@ -16,6 +18,11 @@
 #define VMWARE_BACKDOOR_PMC_APPARENT_TIME	0x10002
 
 #define MAX_FIXED_COUNTERS	3
+static const struct x86_cpu_id vmx_icl_pebs_cpu[] = {
+	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, NULL),
+	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, NULL),
+	{}
+};
 
 struct kvm_event_hw_type_mapping {
 	u8 eventsel;
-- 
2.27.0


  parent reply	other threads:[~2021-08-06 13:39 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-06 13:37 [PATCH V10 00/18] KVM: x86/pmu: Add *basic* support to enable guest PEBS via DS Zhu Lingshan
2021-08-06 13:37 ` [PATCH V10 01/18] perf/core: Use static_call to optimize perf_guest_info_callbacks Zhu Lingshan
2021-08-26 19:59   ` Sean Christopherson
2021-08-27  6:31     ` Like Xu
2021-09-15  1:19     ` Zhu, Lingshan
2021-09-21 23:22       ` Sean Christopherson
2021-08-27 17:23   ` Sean Christopherson
2021-08-06 13:37 ` [PATCH V10 02/18] perf/x86/intel: Add EPT-Friendly PEBS for Ice Lake Server Zhu Lingshan
2021-08-06 13:37 ` [PATCH V10 03/18] perf/x86/intel: Handle guest PEBS overflow PMI for KVM guest Zhu Lingshan
2021-08-06 13:37 ` [PATCH V10 04/18] perf/x86/core: Pass "struct kvm_pmu *" to determine the guest values Zhu Lingshan
2021-08-06 13:37 ` [PATCH V10 05/18] KVM: x86/pmu: Set MSR_IA32_MISC_ENABLE_EMON bit when vPMU is enabled Zhu Lingshan
2021-11-07 10:14   ` Liuxiangdong
2021-11-08  3:06     ` Like Xu
2021-11-08  4:07       ` Liuxiangdong
2021-11-08  4:11         ` Like Xu
2021-11-08  8:27           ` Liuxiangdong
2021-11-08  8:44             ` Like Xu
2021-11-08 10:06               ` Liuxiangdong
2021-08-06 13:37 ` [PATCH V10 06/18] KVM: x86/pmu: Introduce the ctrl_mask value for fixed counter Zhu Lingshan
2021-08-06 13:37 ` [PATCH V10 07/18] x86/perf/core: Add pebs_capable to store valid PEBS_COUNTER_MASK value Zhu Lingshan
2021-08-06 13:37 ` [PATCH V10 08/18] KVM: x86/pmu: Add IA32_PEBS_ENABLE MSR emulation for extended PEBS Zhu Lingshan
2021-08-06 13:37 ` [PATCH V10 09/18] KVM: x86/pmu: Reprogram PEBS event to emulate guest PEBS counter Zhu Lingshan
2021-08-06 13:37 ` Zhu Lingshan [this message]
2021-08-06 13:37 ` [PATCH V10 11/18] KVM: x86/pmu: Add IA32_DS_AREA MSR emulation to support guest DS Zhu Lingshan
2021-08-06 13:37 ` [PATCH V10 12/18] KVM: x86/pmu: Add PEBS_DATA_CFG MSR emulation to support adaptive PEBS Zhu Lingshan
2021-08-06 13:37 ` [PATCH V10 13/18] KVM: x86: Set PEBS_UNAVAIL in IA32_MISC_ENABLE when PEBS is enabled Zhu Lingshan
2021-08-06 13:37 ` [PATCH V10 14/18] KVM: x86/pmu: Move pmc_speculative_in_use() to arch/x86/kvm/pmu.h Zhu Lingshan
2021-08-06 13:37 ` [PATCH V10 15/18] KVM: x86/pmu: Disable guest PEBS temporarily in two rare situations Zhu Lingshan
2021-08-06 13:38 ` [PATCH V10 16/18] KVM: x86/pmu: Add kvm_pmu_cap to optimize perf_get_x86_pmu_capability Zhu Lingshan
2021-08-06 13:38 ` [PATCH V10 17/18] KVM: x86/cpuid: Refactor host/guest CPU model consistency check Zhu Lingshan
2021-08-06 13:38 ` [PATCH V10 18/18] KVM: x86/pmu: Expose CPUIDs feature bits PDCM, DS, DTES64 Zhu Lingshan
2021-08-18  5:27 ` [PATCH V10 00/18] KVM: x86/pmu: Add *basic* support to enable guest PEBS via DS Zhu, Lingshan

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