From: Raghavendra Rao Ananta <rananta@google.com>
To: Paolo Bonzini <pbonzini@redhat.com>, Marc Zyngier <maz@kernel.org>
Cc: Alexandru Elisei <alexandru.elisei@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
James Morse <james.morse@arm.com>,
Peter Shier <pshier@google.com>,
Ricardo Koller <ricarkol@google.com>,
Oliver Upton <oupton@google.com>,
Reiji Watanabe <reijiw@google.com>,
Jing Zhang <jingzhangos@google.com>,
Raghavendra Rao Anata <rananta@google.com>,
kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu
Subject: [PATCH 02/10] KVM: arm64: selftests: Add write_sysreg_s and read_sysreg_s
Date: Fri, 13 Aug 2021 21:12:03 +0000 [thread overview]
Message-ID: <20210813211211.2983293-3-rananta@google.com> (raw)
In-Reply-To: <20210813211211.2983293-1-rananta@google.com>
For register names that are unsupported by the assembler or the ones
without architectural names, add the macros write_sysreg_s and
read_sysreg_s to support them.
The functionality is derived from kvm-unit-tests and kernel's
arch/arm64/include/asm/sysreg.h.
Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
---
.../selftests/kvm/include/aarch64/processor.h | 61 +++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/tools/testing/selftests/kvm/include/aarch64/processor.h b/tools/testing/selftests/kvm/include/aarch64/processor.h
index 14f68bf55036..b4bbce837288 100644
--- a/tools/testing/selftests/kvm/include/aarch64/processor.h
+++ b/tools/testing/selftests/kvm/include/aarch64/processor.h
@@ -115,6 +115,67 @@ void vm_install_exception_handler(struct kvm_vm *vm,
void vm_install_sync_handler(struct kvm_vm *vm,
int vector, int ec, handler_fn handler);
+/*
+ * ARMv8 ARM reserves the following encoding for system registers:
+ * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
+ * C5.2, version:ARM DDI 0487A.f)
+ * [20-19] : Op0
+ * [18-16] : Op1
+ * [15-12] : CRn
+ * [11-8] : CRm
+ * [7-5] : Op2
+ */
+#define Op0_shift 19
+#define Op0_mask 0x3
+#define Op1_shift 16
+#define Op1_mask 0x7
+#define CRn_shift 12
+#define CRn_mask 0xf
+#define CRm_shift 8
+#define CRm_mask 0xf
+#define Op2_shift 5
+#define Op2_mask 0x7
+
+/*
+ * When accessed from guests, the ARM64_SYS_REG() doesn't work since it
+ * generates a different encoding for additional KVM processing, and is
+ * only suitable for userspace to access the register via ioctls.
+ * Hence, define a 'pure' sys_reg() here to generate the encodings as per spec.
+ */
+#define sys_reg(op0, op1, crn, crm, op2) \
+ (((op0) << Op0_shift) | ((op1) << Op1_shift) | \
+ ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
+ ((op2) << Op2_shift))
+
+asm(
+" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
+" .equ .L__reg_num_x\\num, \\num\n"
+" .endr\n"
+" .equ .L__reg_num_xzr, 31\n"
+"\n"
+" .macro mrs_s, rt, sreg\n"
+" .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n"
+" .endm\n"
+"\n"
+" .macro msr_s, sreg, rt\n"
+" .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n"
+" .endm\n"
+);
+
+/*
+ * read_sysreg_s() and write_sysreg_s()'s 'reg' has to be encoded via sys_reg()
+ */
+#define read_sysreg_s(reg) ({ \
+ u64 __val; \
+ asm volatile("mrs_s %0, "__stringify(reg) : "=r" (__val)); \
+ __val; \
+})
+
+#define write_sysreg_s(reg, val) do { \
+ u64 __val = (u64)val; \
+ asm volatile("msr_s "__stringify(reg) ", %x0" : : "rZ" (__val));\
+} while (0)
+
#define write_sysreg(reg, val) \
({ \
u64 __val = (u64)(val); \
--
2.33.0.rc1.237.g0d66db33f3-goog
next prev parent reply other threads:[~2021-08-13 21:12 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-13 21:12 [PATCH 00/10] KVM: arm64: selftests: Introduce arch_timer selftest Raghavendra Rao Ananta
2021-08-13 21:12 ` [PATCH 01/10] KVM: arm64: selftests: Add MMIO readl/writel support Raghavendra Rao Ananta
2021-08-13 21:12 ` Raghavendra Rao Ananta [this message]
2021-08-13 21:12 ` [PATCH 03/10] KVM: arm64: selftests: Add support for cpu_relax Raghavendra Rao Ananta
2021-08-13 21:12 ` [PATCH 04/10] KVM: arm64: selftests: Add basic support for arch_timers Raghavendra Rao Ananta
2021-08-14 9:10 ` Zenghui Yu
2021-08-16 20:01 ` Raghavendra Rao Ananta
2021-08-13 21:12 ` [PATCH 05/10] KVM: arm64: selftests: Add basic support to generate delays Raghavendra Rao Ananta
2021-08-13 21:12 ` [PATCH 06/10] KVM: arm64: selftests: Add support to disable and enable local IRQs Raghavendra Rao Ananta
2021-08-13 21:12 ` [PATCH 07/10] KVM: arm64: selftests: Add support to get the vcpuid from MPIDR_EL1 Raghavendra Rao Ananta
2021-08-13 21:12 ` [PATCH 08/10] KVM: arm64: selftests: Add light-weight spinlock support Raghavendra Rao Ananta
2021-08-13 21:12 ` [PATCH 09/10] KVM: arm64: selftests: Add basic GICv3 support Raghavendra Rao Ananta
2021-08-13 21:12 ` [PATCH 10/10] KVM: arm64: selftests: Add arch_timer test Raghavendra Rao Ananta
2021-08-16 12:15 ` [PATCH 00/10] KVM: arm64: selftests: Introduce arch_timer selftest Andrew Jones
2021-08-16 20:56 ` Raghavendra Rao Ananta
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