From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45AB6C433EF for ; Wed, 12 Jan 2022 04:11:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345995AbiALELL (ORCPT ); Tue, 11 Jan 2022 23:11:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229770AbiALELK (ORCPT ); Tue, 11 Jan 2022 23:11:10 -0500 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9715C06173F; Tue, 11 Jan 2022 20:11:10 -0800 (PST) Received: by mail-pj1-x1030.google.com with SMTP id a1-20020a17090a688100b001b3fd52338eso1303854pjd.1; Tue, 11 Jan 2022 20:11:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=L3zit3ZisIykD+J7W/w/LdcsvaZddg/hlkAzNk64CDc=; b=YLhkGzWqfbeaAjok250HgZg7AcR/GfWcLFcx6ZfXbajWrwh2C9C9i8Wb6lhRQVA1O1 kE0+HOXJ0wng8YQ1vv+ooZ5okHR5nJhq2Uja+tPjqAz/plWUMI0mvj7FSNfDJBoBTZRn C2y6/3gDaJxKGdguaxlIrCtukGfG61M8bTlRyu0cfHa3YUkD2+rPGPEEzpXTIC9+tgD/ +6GavfrYSaSu6LeAHMOX9gk0S4YjkWDDktwkYaa4QfJq1FFhMK5jvhLOzn6U3gDvaS+m wYaLD1q91mz+byg5dab3B/386DZrwYAY2VZkx9KZtwfnwSPyTHxIG6WsHdDL1+yWWuJ+ PSbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=L3zit3ZisIykD+J7W/w/LdcsvaZddg/hlkAzNk64CDc=; b=nt/DSZ4Poo3zsA61YlS5tqtUhO0Jbx2pw3D7/8AJWzURZ43NJd13PkO7KEEliWadQY 7B4+EwycaQesjFHDA98v9HaTnX668X/NnNAew5DMHLFqRpRLocKNPrR3+2rlrV2bw2vV QirU8zU6gm48BvlSYFGOSbstInoeLQ/lqxkR5rg2Sdg3Mqk0C32HMNufgCSPtjK5wFZs o5ublUK0cn4+8KIhmr5iXX0HDG/0McQoJf60b9eKUGaMXE0TyTd/l12L5E8sty/16lFZ CRD/asP+Yc/RfLKhVAFj1TVoIkdPhefzu0uL2CyT2Kwu4djESmxa0OIgxuJTt0Vg1NYT zkwg== X-Gm-Message-State: AOAM5328FPHG79ZWgsflrIrPV7n7mvlCsyNVUdnFiagRGk6wxiXgbeR3 iPusqBNlTrirNDwF41yH4U0= X-Google-Smtp-Source: ABdhPJzg7u5LABeMdTWZ8i7PcbMUHLE5C7HuaKTE7xqKYfob+C5Is9xhK7sRZX7UgnreRzl7pNrGww== X-Received: by 2002:a17:902:b681:b0:14a:9cc:d9a3 with SMTP id c1-20020a170902b68100b0014a09ccd9a3mr7712222pls.121.1641960670257; Tue, 11 Jan 2022 20:11:10 -0800 (PST) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id h5sm7117718pfo.57.2022.01.11.20.11.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jan 2022 20:11:09 -0800 (PST) From: Like Xu X-Google-Original-From: Like Xu To: Paolo Bonzini , Sean Christopherson Cc: Jim Mattson , Wanpeng Li , Vitaly Kuznetsov , Joerg Roedel , x86@kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3] KVM: x86/pt: Ignore all unknown Intel PT capabilities Date: Wed, 12 Jan 2022 12:11:00 +0800 Message-Id: <20220112041100.26769-1-likexu@tencent.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu Some of the new Intel PT capabilities (e.g. SDM Vol3, 32.2.4 Event Tracing, exposes details about the asynchronous events, when they are generated, and when their corresponding software event handler completes execution) cannot be safely and fully emulated by the KVM, especially emulating the simultaneous writing of guest PT packets generated by the KVM to the guest PT buffer. For KVM, it's better to advertise currently supported features based on the "static struct pt_cap_desc" implemented in the host PT driver and ignore _all_ unknown features before they have been investigated one by one and supported in a safe manner, leaving the rest as system-wide-only tracing capabilities. Suggested-by: Paolo Bonzini Signed-off-by: Like Xu --- v2 -> v3 Changelog: - Remove unnecessary comment; (Sean) - Add a #define in the pt header for better self-documentin; (Sean) - Add validity checks to CPUID E{A|B|C|D}X; (Sean) Previous: https://lore.kernel.org/kvm/20220110034747.30498-1-likexu@tencent.com/ arch/x86/include/asm/intel_pt.h | 6 ++++++ arch/x86/kvm/cpuid.c | 6 +++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/intel_pt.h b/arch/x86/include/asm/intel_pt.h index ebe8d2ea44fe..da94d0eeb9df 100644 --- a/arch/x86/include/asm/intel_pt.h +++ b/arch/x86/include/asm/intel_pt.h @@ -24,6 +24,12 @@ enum pt_capabilities { PT_CAP_psb_periods, }; +#define GUEST_SUPPORTED_CPUID_14_EBX \ + (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5)) + +#define GUEST_SUPPORTED_CPUID_14_ECX \ + (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(31)) + #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL) void cpu_emergency_stop_pt(void); extern u32 intel_pt_validate_hw_cap(enum pt_capabilities cap); diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 0b920e12bb6d..be8c9170f98e 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "cpuid.h" #include "lapic.h" #include "mmu.h" @@ -900,7 +901,10 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) entry->eax = entry->ebx = entry->ecx = entry->edx = 0; break; } - + entry->eax = min(entry->eax, 1u); + entry->ebx &= GUEST_SUPPORTED_CPUID_14_EBX; + entry->ecx &= GUEST_SUPPORTED_CPUID_14_ECX; + entry->edx = 0; for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { if (!do_host_cpuid(array, function, i)) goto out; -- 2.33.1