From: Like Xu <like.xu.linux@gmail.com>
To: Sean Christopherson <seanjc@google.com>,
Paolo Bonzini <pbonzini@redhat.com>
Cc: Jim Mattson <jmattson@google.com>,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
Like Xu <likexu@tencent.com>
Subject: [PATCH 2/7] perf/x86/core: Completely disable guest PEBS via guest's global_ctrl
Date: Wed, 13 Jul 2022 20:25:01 +0800 [thread overview]
Message-ID: <20220713122507.29236-3-likexu@tencent.com> (raw)
In-Reply-To: <20220713122507.29236-1-likexu@tencent.com>
From: Like Xu <likexu@tencent.com>
When a guest PEBS counter is cross-mapped by a host counter, software
will remove the corresponding bit in the arr[global_ctrl].guest and
expect hardware to perform a change of state "from enable to disable"
via the msr_slot[] switch during the vmx transaction.
The real world is that if user adjust the counter overflow value small
enough, it still opens a tiny race window for the previously PEBS-enabled
counter to write cross-mapped PEBS records into the guest's PEBS buffer,
when arr[global_ctrl].guest has been prioritised (switch_msr_special stuff)
to switch into the enabled state, while the arr[pebs_enable].guest has not.
Close this window by clearing invalid bits in the arr[global_ctrl].guest.
Fixes: 854250329c02 ("KVM: x86/pmu: Disable guest PEBS temporarily in two rare situations")
Signed-off-by: Like Xu <likexu@tencent.com>
---
arch/x86/events/intel/core.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index e46fd496187b..495ac447bb3a 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4052,8 +4052,9 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
/* Disable guest PEBS if host PEBS is enabled. */
arr[pebs_enable].guest = 0;
} else {
- /* Disable guest PEBS for cross-mapped PEBS counters. */
+ /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */
arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask;
+ arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask;
/* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */
arr[global_ctrl].guest |= arr[pebs_enable].guest;
}
--
2.37.0
next prev parent reply other threads:[~2022-07-13 12:25 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-13 12:24 [PATCH 0/7] KVM: x86/pmu: Fix some corner cases including Intel PEBS Like Xu
2022-07-13 12:25 ` [PATCH 1/7] perf/x86/core: Update x86_pmu.pebs_capable for ICELAKE_{X,D} Like Xu
2022-07-13 12:25 ` Like Xu [this message]
2022-07-13 12:25 ` [PATCH 3/7] KVM: x86/pmu: Avoid setting BIT_ULL(-1) to pmu->host_cross_mapped_mask Like Xu
2022-07-21 0:45 ` Sean Christopherson
2022-07-21 2:02 ` Like Xu
2022-07-21 18:27 ` Sean Christopherson
2022-07-13 12:25 ` [PATCH 4/7] KVM: x86/pmu: Not to generate PEBS records for emulated instructions Like Xu
2022-07-21 0:51 ` Sean Christopherson
2022-07-21 2:22 ` Like Xu
2022-07-13 12:25 ` [PATCH 5/7] KVM: x86/pmu: Avoid using PEBS perf_events for normal counters Like Xu
2022-07-13 12:25 ` [PATCH 6/7] KVM: x86/pmu: Defer reprogram_counter() to kvm_pmu_handle_event() Like Xu
2022-07-13 12:25 ` [PATCH 7/7] KVM: x86/pmu: Defer counter emulated overflow via pmc->stale_counter Like Xu
2022-07-13 12:25 ` [kvm-unit-tests PATCH] x86: Add tests for Guest Processor Event Based Sampling (PEBS) Like Xu
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