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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT038.mail.protection.outlook.com (10.13.174.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5525.11 via Frontend Transport; Wed, 10 Aug 2022 06:14:41 +0000 Received: from BLR-5CG113396M.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 10 Aug 2022 01:14:06 -0500 From: Santosh Shukla To: Paolo Bonzini CC: Sean Christopherson , Vitaly Kuznetsov , Jim Mattson , Joerg Roedel , Tom Lendacky , , , , Subject: [PATCHv3 3/8] KVM: SVM: Add VNMI support in get/set_nmi_mask Date: Wed, 10 Aug 2022 11:42:21 +0530 Message-ID: <20220810061226.1286-4-santosh.shukla@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220810061226.1286-1-santosh.shukla@amd.com> References: <20220810061226.1286-1-santosh.shukla@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c02be749-98c8-4c3e-c3e5-08da7a979ca5 X-MS-TrafficTypeDiagnostic: DM6PR12MB3579:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Aug 2022 06:14:41.1075 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c02be749-98c8-4c3e-c3e5-08da7a979ca5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3579 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org VMCB intr_ctrl bit12 (V_NMI_MASK) is set by the processor when handling NMI in guest and is cleared after the NMI is handled. Treat V_NMI_MASK as read-only in the hypervisor except for the SMM case where hypervisor before entring and after leaving SMM mode requires to set and unset V_NMI_MASK. Adding API(get_vnmi_vmcb) in order to return the correct vmcb for L1 or L2, and also API(clear/set_vnmi_mask) to clear and set mask. Signed-off-by: Santosh Shukla --- v3: * Handle SMM case * Added set/clear_vnmi_mask() API. v2: - Added get_vnmi_vmcb API to return vmcb for l1 and l2. - Use get_vnmi_vmcb to get correct vmcb in func - is_vnmi_enabled/_mask_set() - removed vnmi check from is_vnmi_enabled() func. arch/x86/kvm/svm/svm.c | 17 +++++++++++++- arch/x86/kvm/svm/svm.h | 52 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 0259b909ed16..f0ac197fd965 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -3621,13 +3621,28 @@ static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection) static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) { - return !!(vcpu->arch.hflags & HF_NMI_MASK); + struct vcpu_svm *svm = to_svm(vcpu); + + if (is_vnmi_enabled(svm)) + return is_vnmi_mask_set(svm); + else + return !!(vcpu->arch.hflags & HF_NMI_MASK); } static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) { struct vcpu_svm *svm = to_svm(vcpu); + if (is_vnmi_enabled(svm)) { + if (is_smm(vcpu)) { + if (masked) + set_vnmi_mask(svm); + else + clear_vnmi_mask(svm); + } + return; + } + if (masked) { vcpu->arch.hflags |= HF_NMI_MASK; if (!sev_es_guest(vcpu->kvm)) diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 6a7686bf6900..cc98ec7bd119 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -35,6 +35,7 @@ extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; extern bool npt_enabled; extern int vgif; extern bool intercept_smi; +extern bool vnmi; enum avic_modes { AVIC_MODE_NONE = 0, @@ -532,6 +533,57 @@ static inline bool is_x2apic_msrpm_offset(u32 offset) (msr < (APIC_BASE_MSR + 0x100)); } +static inline struct vmcb *get_vnmi_vmcb(struct vcpu_svm *svm) +{ + if (!vnmi) + return NULL; + + if (is_guest_mode(&svm->vcpu)) + return svm->nested.vmcb02.ptr; + else + return svm->vmcb01.ptr; +} + +static inline bool is_vnmi_enabled(struct vcpu_svm *svm) +{ + struct vmcb *vmcb = get_vnmi_vmcb(svm); + + if (vmcb) + return !!(vmcb->control.int_ctl & V_NMI_ENABLE); + else + return false; +} + +static inline bool is_vnmi_mask_set(struct vcpu_svm *svm) +{ + struct vmcb *vmcb = get_vnmi_vmcb(svm); + + if (vmcb) + return !!(vmcb->control.int_ctl & V_NMI_MASK); + else + return false; +} + +static inline void set_vnmi_mask(struct vcpu_svm *svm) +{ + struct vmcb *vmcb = get_vnmi_vmcb(svm); + + if (vmcb) + vmcb->control.int_ctl |= V_NMI_MASK; + else + svm->vcpu.arch.hflags |= HF_GIF_MASK; +} + +static inline void clear_vnmi_mask(struct vcpu_svm *svm) +{ + struct vmcb *vmcb = get_vnmi_vmcb(svm); + + if (vmcb) + vmcb->control.int_ctl &= ~V_NMI_MASK; + else + svm->vcpu.arch.hflags &= ~HF_GIF_MASK; +} + /* svm.c */ #define MSR_INVALID 0xffffffffU -- 2.25.1