From: Vitaly Kuznetsov <vkuznets@redhat.com>
To: kvm@vger.kernel.org, Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>
Cc: Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>,
Michael Kelley <mikelley@microsoft.com>,
Maxim Levitsky <mlevitsk@redhat.com>,
linux-hyperv@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v5 1/7] x86/hyperv: Add HV_EXPOSE_INVARIANT_TSC define
Date: Thu, 13 Oct 2022 11:58:43 +0200 [thread overview]
Message-ID: <20221013095849.705943-2-vkuznets@redhat.com> (raw)
In-Reply-To: <20221013095849.705943-1-vkuznets@redhat.com>
Avoid open coding BIT(0) of HV_X64_MSR_TSC_INVARIANT_CONTROL by adding
a dedicated define. While there's only one user at this moment, the
upcoming KVM implementation of Hyper-V Invariant TSC feature will need
to use it as well.
Reviewed-by: Michael Kelley <mikelley@microsoft.com>
Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
---
arch/x86/include/asm/hyperv-tlfs.h | 3 +++
arch/x86/kernel/cpu/mshyperv.c | 2 +-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/hyperv-tlfs.h b/arch/x86/include/asm/hyperv-tlfs.h
index 3089ec352743..196a8945bcd7 100644
--- a/arch/x86/include/asm/hyperv-tlfs.h
+++ b/arch/x86/include/asm/hyperv-tlfs.h
@@ -253,6 +253,9 @@ enum hv_isolation_type {
/* TSC invariant control */
#define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118
+/* HV_X64_MSR_TSC_INVARIANT_CONTROL bits */
+#define HV_EXPOSE_INVARIANT_TSC BIT_ULL(0)
+
/* Register name aliases for temporary compatibility */
#define HV_X64_MSR_STIMER0_COUNT HV_REGISTER_STIMER0_COUNT
#define HV_X64_MSR_STIMER0_CONFIG HV_REGISTER_STIMER0_CONFIG
diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c
index 831613959a92..e402923800d7 100644
--- a/arch/x86/kernel/cpu/mshyperv.c
+++ b/arch/x86/kernel/cpu/mshyperv.c
@@ -388,7 +388,7 @@ static void __init ms_hyperv_init_platform(void)
* setting of this MSR bit should happen before init_intel()
* is called.
*/
- wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, 0x1);
+ wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, HV_EXPOSE_INVARIANT_TSC);
setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
}
--
2.37.3
next prev parent reply other threads:[~2022-10-13 9:59 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-13 9:58 [PATCH v5 0/7] KVM: x86: Hyper-V invariant TSC control feature Vitaly Kuznetsov
2022-10-13 9:58 ` Vitaly Kuznetsov [this message]
2022-10-13 9:58 ` [PATCH v5 2/7] KVM: x86: Add a KVM-only leaf for CPUID_8000_0007_EDX Vitaly Kuznetsov
2022-10-13 9:58 ` [PATCH v5 3/7] KVM: x86: Hyper-V invariant TSC control Vitaly Kuznetsov
2022-10-13 9:58 ` [PATCH v5 4/7] KVM: selftests: Rename 'msr->available' to 'msr->fault_exepected' in hyperv_features test Vitaly Kuznetsov
2022-10-13 9:58 ` [PATCH v5 5/7] KVM: selftests: Convert hyperv_features test to using KVM_X86_CPU_FEATURE() Vitaly Kuznetsov
2022-10-13 9:58 ` [PATCH v5 6/7] KVM: selftests: Test that values written to Hyper-V MSRs are preserved Vitaly Kuznetsov
2022-10-13 9:58 ` [PATCH v5 7/7] KVM: selftests: Test Hyper-V invariant TSC control Vitaly Kuznetsov
2022-10-14 20:04 ` [PATCH v5 0/7] KVM: x86: Hyper-V invariant TSC control feature Sean Christopherson
2022-11-22 15:43 ` Vitaly Kuznetsov
2022-12-24 11:04 ` Paolo Bonzini
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