From: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
To: qemu-devel@nongnu.org
Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk,
kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com,
palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, pbonzini@redhat.com,
philipp.tomsich@vrull.eu, kvm@vger.kernel.org,
Max Chou <max.chou@sifive.com>
Subject: [PATCH 41/45] crypto: Create sm4_subword
Date: Fri, 10 Mar 2023 09:12:11 +0000 [thread overview]
Message-ID: <20230310091215.931644-42-lawrence.hunter@codethink.co.uk> (raw)
In-Reply-To: <20230310091215.931644-1-lawrence.hunter@codethink.co.uk>
From: Max Chou <max.chou@sifive.com>
- Share sm4_subword between different targets.
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
include/crypto/sm4.h | 8 ++++++++
target/arm/tcg/crypto_helper.c | 10 ++--------
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
index 9bd3ebc62e..de8245d8a7 100644
--- a/include/crypto/sm4.h
+++ b/include/crypto/sm4.h
@@ -3,4 +3,12 @@
extern const uint8_t sm4_sbox[256];
+static inline uint32_t sm4_subword(uint32_t word)
+{
+ return sm4_sbox[word & 0xff] |
+ sm4_sbox[(word >> 8) & 0xff] << 8 |
+ sm4_sbox[(word >> 16) & 0xff] << 16 |
+ sm4_sbox[(word >> 24) & 0xff] << 24;
+}
+
#endif
diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c
index d28690321f..58e6c4f779 100644
--- a/target/arm/tcg/crypto_helper.c
+++ b/target/arm/tcg/crypto_helper.c
@@ -707,10 +707,7 @@ static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
CR_ST_WORD(d, (i + 3) % 4) ^
CR_ST_WORD(n, i);
- t = sm4_sbox[t & 0xff] |
- sm4_sbox[(t >> 8) & 0xff] << 8 |
- sm4_sbox[(t >> 16) & 0xff] << 16 |
- sm4_sbox[(t >> 24) & 0xff] << 24;
+ t = sm4_subword(t);
CR_ST_WORD(d, i) ^= t ^ rol32(t, 2) ^ rol32(t, 10) ^ rol32(t, 18) ^
rol32(t, 24);
@@ -744,10 +741,7 @@ static void do_crypto_sm4ekey(uint64_t *rd, uint64_t *rn, uint64_t *rm)
CR_ST_WORD(d, (i + 3) % 4) ^
CR_ST_WORD(m, i);
- t = sm4_sbox[t & 0xff] |
- sm4_sbox[(t >> 8) & 0xff] << 8 |
- sm4_sbox[(t >> 16) & 0xff] << 16 |
- sm4_sbox[(t >> 24) & 0xff] << 24;
+ t = sm4_subword(t);
CR_ST_WORD(d, i) ^= t ^ rol32(t, 13) ^ rol32(t, 23);
}
--
2.39.2
next prev parent reply other threads:[~2023-03-10 9:45 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-10 9:11 [PATCH 00/45] Add RISC-V vector cryptographic instruction set support Lawrence Hunter
2023-03-10 9:11 ` [PATCH 01/45] target/riscv: Add zvkb cpu property Lawrence Hunter
2023-03-10 9:11 ` [PATCH 02/45] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-03-10 9:11 ` [PATCH 03/45] target/riscv: Add vclmul.vv decoding, translation and execution support Lawrence Hunter
2023-03-10 9:11 ` [PATCH 04/45] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-03-12 23:40 ` Wilfred Mallawa
2023-03-10 9:11 ` [PATCH 05/45] target/riscv: Add vclmul.vx decoding, translation and execution support Lawrence Hunter
2023-03-10 9:11 ` [PATCH 06/45] target/riscv: Add vclmulh.vv " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 07/45] target/riscv: Add vclmulh.vx " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 08/45] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-03-10 9:11 ` [PATCH 09/45] qemu/bitops.h: Limit rotate amounts Lawrence Hunter
2023-03-10 9:11 ` [PATCH 10/45] target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] decoding, translation and execution support Lawrence Hunter
2023-03-10 9:11 ` [PATCH 11/45] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-03-10 9:11 ` [PATCH 12/45] target/riscv: Add vbrev8.v decoding, translation and execution support Lawrence Hunter
2023-03-10 9:11 ` [PATCH 13/45] target/riscv: Add vrev8.v " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 14/45] target/riscv: Add vandn.[vv,vx] " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 15/45] target/riscv: Expose zvkb cpu property Lawrence Hunter
2023-03-10 9:11 ` [PATCH 16/45] target/riscv: Add zvkned " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 17/45] target/riscv: Add vaesef.vv decoding, translation and execution support Lawrence Hunter
2023-03-10 9:11 ` [PATCH 18/45] target/riscv: Add vaesef.vs " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 19/45] target/riscv: Add vaesdf.vv " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 20/45] target/riscv: Add vaesdf.vs " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 21/45] target/riscv: Add vaesdm.vv " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 22/45] target/riscv: Add vaesdm.vs " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 23/45] target/riscv: Add vaesz.vs " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 24/45] target/riscv: Add vaesem.vv " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 25/45] target/riscv: Add vaesem.vs " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 26/45] target/riscv: Add vaeskf1.vi " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 27/45] target/riscv: Add vaeskf2.vi " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 28/45] target/riscv: Expose zvkned cpu property Lawrence Hunter
2023-03-10 9:11 ` [PATCH 29/45] target/riscv: Add zvknh cpu properties Lawrence Hunter
2023-03-10 9:12 ` [PATCH 30/45] target/riscv: Add vsha2ms.vv decoding, translation and execution support Lawrence Hunter
2023-03-10 9:12 ` [PATCH 31/45] target/riscv: Add vsha2c[hl].vv " Lawrence Hunter
2023-03-10 9:12 ` [PATCH 32/45] target/riscv: Expose zvknh cpu properties Lawrence Hunter
2023-03-10 9:12 ` [PATCH 33/45] target/riscv: Add zvksh cpu property Lawrence Hunter
2023-03-10 9:12 ` [PATCH 34/45] target/riscv: Add vsm3me.vv decoding, translation and execution support Lawrence Hunter
2023-03-10 9:12 ` [PATCH 35/45] target/riscv: Add vsm3c.vi " Lawrence Hunter
2023-03-10 9:12 ` [PATCH 36/45] target/riscv: Expose zvksh cpu property Lawrence Hunter
2023-03-10 9:12 ` [PATCH 37/45] target/riscv: Add zvkg " Lawrence Hunter
2023-03-10 9:12 ` [PATCH 38/45] target/riscv: Add vgmul.vv decoding, translation and execution support Lawrence Hunter
2023-03-10 9:12 ` [PATCH 39/45] target/riscv: Add vghsh.vv " Lawrence Hunter
2023-03-10 9:12 ` [PATCH 40/45] target/riscv: Expose zvkg cpu property Lawrence Hunter
2023-03-10 9:12 ` Lawrence Hunter [this message]
2023-03-10 9:12 ` [PATCH 42/45] crypto: Add SM4 constant parameter CK Lawrence Hunter
2023-03-10 9:12 ` [PATCH 43/45] target/riscv: Add zvksed cfg property Lawrence Hunter
2023-03-10 9:12 ` [PATCH 44/45] target/riscv: Add Zvksed support Lawrence Hunter
2023-03-10 9:12 ` [PATCH 45/45] target/riscv: Expose Zvksed property Lawrence Hunter
2023-03-21 12:02 ` [PATCH 00/45] Add RISC-V vector cryptographic instruction set support Christoph Müllner
2023-03-23 11:34 ` Lawrence Hunter
2023-03-23 11:36 ` Christoph Müllner
2023-03-10 16:03 Lawrence Hunter
2023-03-10 16:03 ` [PATCH 41/45] crypto: Create sm4_subword Lawrence Hunter
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