From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 129FAC6FA99 for ; Fri, 10 Mar 2023 16:06:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231377AbjCJQGu (ORCPT ); Fri, 10 Mar 2023 11:06:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230408AbjCJQGE (ORCPT ); Fri, 10 Mar 2023 11:06:04 -0500 Received: from imap5.colo.codethink.co.uk (imap5.colo.codethink.co.uk [78.40.148.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37DCD58B59 for ; Fri, 10 Mar 2023 08:04:09 -0800 (PST) Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pafDk-00H4ad-K9; Fri, 10 Mar 2023 16:03:52 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 13/45] target/riscv: Add vrev8.v decoding, translation and execution support Date: Fri, 10 Mar 2023 16:03:14 +0000 Message-Id: <20230310160346.1193597-14-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230310160346.1193597-1-lawrence.hunter@codethink.co.uk> References: <20230310160346.1193597-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h | 4 ++++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 + target/riscv/vcrypto_helper.c | 11 +++++++++++ 4 files changed, 17 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 625f9872d0..b4baa22692 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1169,6 +1169,10 @@ DEF_HELPER_6(vrol_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrol_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrol_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_5(vrev8_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vrev8_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vrev8_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vrev8_v_d, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_b, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_w, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 87473a77c0..bdefcd3fa2 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -922,3 +922,4 @@ vror_vv 010100 . ..... ..... 000 ..... 1010111 @r_vm vror_vx 010100 . ..... ..... 100 ..... 1010111 @r_vm vror_vi 01010. . ..... ..... 011 ..... 1010111 @r2_zimm6 vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm +vrev8_v 010010 . ..... 01001 010 ..... 1010111 @r2_vm diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn_trans/trans_rvzvkb.c.inc index 7cd114ae71..77ba8bc713 100644 --- a/target/riscv/insn_trans/trans_rvzvkb.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc @@ -183,3 +183,4 @@ static bool vxrev8_check(DisasContext *s, arg_rmr *a) } GEN_OPIV_TRANS(vbrev8_v, vxrev8_check) +GEN_OPIV_TRANS(vrev8_v, vxrev8_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 5d2a995de6..ecf21c50f8 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/host-utils.h" #include "qemu/bitops.h" +#include "qemu/bswap.h" #include "cpu.h" #include "exec/memop.h" #include "exec/exec-all.h" @@ -114,3 +115,13 @@ GEN_VEXT_V(vbrev8_v_b, 1) GEN_VEXT_V(vbrev8_v_h, 2) GEN_VEXT_V(vbrev8_v_w, 4) GEN_VEXT_V(vbrev8_v_d, 8) + +#define DO_IDENTITY(a) (a) +RVVCALL(OPIVV1, vrev8_v_b, OP_UU_B, H1, H1, DO_IDENTITY) +RVVCALL(OPIVV1, vrev8_v_h, OP_UU_H, H2, H2, bswap16) +RVVCALL(OPIVV1, vrev8_v_w, OP_UU_W, H4, H4, bswap32) +RVVCALL(OPIVV1, vrev8_v_d, OP_UU_D, H8, H8, bswap64) +GEN_VEXT_V(vrev8_v_b, 1) +GEN_VEXT_V(vrev8_v_h, 2) +GEN_VEXT_V(vrev8_v_w, 4) +GEN_VEXT_V(vrev8_v_d, 8) -- 2.39.2