From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA654C7618A for ; Sun, 19 Mar 2023 08:37:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229997AbjCSIhp (ORCPT ); Sun, 19 Mar 2023 04:37:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41400 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229490AbjCSIhn (ORCPT ); Sun, 19 Mar 2023 04:37:43 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2C4623C54 for ; Sun, 19 Mar 2023 01:37:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1679215061; x=1710751061; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QlvC8KjyOonSyQURFfiETkdw4gYK4IaymmJRQr/dpF8=; b=J6PyrmlDzD23msCNejRPKxcGRrBRwAUsWtCYRmcxBlgz4kzlE46kh1YE aJBb+ZnhS/tLEYc4xO2oFn/XB6uP6mjEH127hGZUaqXGcORvPfIB+Wvbz GTBCJ3jnmezozDtog0Joz3xfo7tTlP4irXKz0i8dS/QARlVQDcboabiz0 JgmWxcxwTo0mRc37etJVw76Cnv2IcdhzRAE4I5tA1bk1g7R7OYcekZAAK jMudVVeY24Wg+88g+smgNxTR5UZIAe3tTB1/fO3m/Ds8yImYYMXLBiQG7 u/zj/2MEkz8xwAmpJnOxNbUUnqBhTaj9sGREE+eBIPErSHUaMeiPFWrmt g==; X-IronPort-AV: E=McAfee;i="6600,9927,10653"; a="424767128" X-IronPort-AV: E=Sophos;i="5.98,273,1673942400"; d="scan'208";a="424767128" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 01:37:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10653"; a="769853311" X-IronPort-AV: E=Sophos;i="5.98,273,1673942400"; d="scan'208";a="769853311" Received: from binbinwu-mobl.ccr.corp.intel.com ([10.254.209.111]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 01:37:40 -0700 From: Binbin Wu To: kvm@vger.kernel.org, seanjc@google.com, pbonzini@redhat.com Cc: chao.gao@intel.com, robert.hu@linux.intel.com, binbin.wu@linux.intel.com Subject: [kvm-unit-tests PATCH v2 1/4] x86: Allow setting of CR3 LAM bits if LAM supported Date: Sun, 19 Mar 2023 16:37:29 +0800 Message-Id: <20230319083732.29458-2-binbin.wu@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230319083732.29458-1-binbin.wu@linux.intel.com> References: <20230319083732.29458-1-binbin.wu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org If LAM is supported, VM entry allows CR3.LAM_U48 (bit 62) and CR3.LAM_U57 (bit 61) to be set in CR3 field. Change the test result expectations when setting CR3.LAM_U48 or CR3.LAM_U57 on vmlaunch tests when LAM is supported. Signed-off-by: Binbin Wu --- lib/x86/processor.h | 2 ++ x86/vmx_tests.c | 6 +++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/lib/x86/processor.h b/lib/x86/processor.h index 3d58ef7..8373bbe 100644 --- a/lib/x86/processor.h +++ b/lib/x86/processor.h @@ -55,6 +55,8 @@ #define X86_CR0_PG BIT(X86_CR0_PG_BIT) #define X86_CR3_PCID_MASK GENMASK(11, 0) +#define X86_CR3_LAM_U57_BIT (61) +#define X86_CR3_LAM_U48_BIT (62) #define X86_CR4_VME_BIT (0) #define X86_CR4_VME BIT(X86_CR4_VME_BIT) diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c index 7bba816..1be22ac 100644 --- a/x86/vmx_tests.c +++ b/x86/vmx_tests.c @@ -7000,7 +7000,11 @@ static void test_host_ctl_regs(void) cr3 = cr3_saved | (1ul << i); vmcs_write(HOST_CR3, cr3); report_prefix_pushf("HOST_CR3 %lx", cr3); - test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); + if (this_cpu_has(X86_FEATURE_LAM) && + ((i==X86_CR3_LAM_U57_BIT) || (i==X86_CR3_LAM_U48_BIT))) + test_vmx_vmlaunch(0); + else + test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); report_prefix_pop(); } -- 2.25.1